Weimin Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79091?usp=email )
Change subject: mb/google/brya/var/anraggar: Modify LTE GPIO port of A8&D6 ......................................................................
mb/google/brya/var/anraggar: Modify LTE GPIO port of A8&D6
Enable Bluetooth USB port for CNVi WLAN.
BUG=b:304920262 TEST=LTE function verification is normal
Change-Id: I9847029fc7cc5b2c13f2674e4ce26ed9d4f84ae7 Signed-off-by: wuweimin wuweimin@huaqin.corp-partner.google.com --- M src/mainboard/google/brya/variants/anraggar/gpio.c M src/mainboard/google/brya/variants/anraggar/overridetree.cb 2 files changed, 29 insertions(+), 21 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/79091/1
diff --git a/src/mainboard/google/brya/variants/anraggar/gpio.c b/src/mainboard/google/brya/variants/anraggar/gpio.c index 6eac21a..f74cfbe 100644 --- a/src/mainboard/google/brya/variants/anraggar/gpio.c +++ b/src/mainboard/google/brya/variants/anraggar/gpio.c @@ -9,6 +9,8 @@ static const struct pad_config override_gpio_table[] = { /* A7 : NC ==> LTE_Present */ PAD_CFG_GPI(GPP_A7, NONE, DEEP), + /* A8 : GPP_A8 ==> WWAN_RF_DISABLE_ODL */ + PAD_CFG_GPO(GPP_A8, 1, DEEP), /* A18 : NC ==> HDMI_HPD_SRC*/ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
@@ -47,7 +49,7 @@ /* F12 : GSXDOUT ==> WWAN_RST_L */ PAD_CFG_GPO_LOCK(GPP_F12, 1, LOCK_CONFIG), /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD ==> EN_PP2800_AVDD*/ - PAD_CFG_GPO(GPP_F18, 0, DEEP), + PAD_CFG_GPO(GPP_F18, 1, DEEP), /* F23 : V1P05_CTRL ==> V1P05EXT_CTRL ==> NC*/ PAD_NC_LOCK(GPP_F23, NONE, LOCK_CONFIG),
@@ -80,8 +82,8 @@ PAD_CFG_GPO(GPP_F11, 1, DEEP), /* F12 : GSXDOUT ==> WWAN_RST_L */ PAD_CFG_GPO(GPP_F12, 0, DEEP), - /* F16 : NC ==> WWAN_PWR_ENABLE */ - PAD_CFG_GPO(GPP_F16, 1, DEEP), + /* D6 : NC ==> WWAN_PWR_ENABLE */ + PAD_CFG_GPO(GPP_D6, 1, DEEP),
/* H4 : I2C0_SDA ==> SOC_I2C_GSC_SDA */ PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), diff --git a/src/mainboard/google/brya/variants/anraggar/overridetree.cb b/src/mainboard/google/brya/variants/anraggar/overridetree.cb index bf56363..205db65 100644 --- a/src/mainboard/google/brya/variants/anraggar/overridetree.cb +++ b/src/mainboard/google/brya/variants/anraggar/overridetree.cb @@ -162,7 +162,7 @@ register "device_type" = "INTEL_ACPI_CAMERA_CIO2"
register "cio2_num_ports" = "1" - register "cio2_lanes_used" = "{2}" # 2 CSI Camera lanes are used + register "cio2_lanes_used" = "{4}" # 4 CSI Camera lanes are used register "cio2_lane_endpoint[0]" = ""^I2C2.CAM0"" register "cio2_prt[0]" = "1" device generic 0 on end @@ -199,18 +199,17 @@ end device ref i2c2 on chip drivers/intel/mipi_camera - register "acpi_hid" = ""OVTI5675"" + register "acpi_hid" = ""OVTIDB10"" register "acpi_uid" = "0" register "acpi_name" = ""CAM0"" - register "chip_name" = ""Ov 5675 Camera"" + register "chip_name" = ""Ov 13b10 Camera"" register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
- register "ssdb.lanes_used" = "2" - register "ssdb.link_used" = "1" + register "ssdb.lanes_used" = "4" register "ssdb.vcm_type" = "0x0C" register "vcm_name" = ""VCM0"" register "num_freq_entries" = "1" - register "link_freq[0]" = "DEFAULT_LINK_FREQ" + register "link_freq[0]" = "560 * MHz" register "remote_name" = ""IPU0""
register "has_power_resource" = "1" @@ -219,16 +218,15 @@ register "clk_panel.clks[0].freq" = "FREQ_19_2_MHZ"
register "gpio_panel.gpio[0].gpio_num" = "GPP_D15" # EN_PP2800_WCAM_X - register "gpio_panel.gpio[1].gpio_num" = "GPP_D16" # EN_PP1800_PP1200_WCAM_X + register "gpio_panel.gpio[1].gpio_num" = "GPP_D16" # EN_PP1200_WCAM_X register "gpio_panel.gpio[2].gpio_num" = "GPP_D3" # WCAM_RST_L
#_ON - register "on_seq.ops_cnt" = "5" + register "on_seq.ops_cnt" = "4" register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)" register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 5)" register "on_seq.ops[2]" = "SEQ_OPS_GPIO_ENABLE(1, 5)" - register "on_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(2, 5)" - register "on_seq.ops[4]" = "SEQ_OPS_GPIO_ENABLE(2, 5)" + register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(2, 5)"
#_OFF register "off_seq.ops_cnt" = "4" @@ -240,30 +238,38 @@ device i2c 36 on end end chip drivers/intel/mipi_camera - register "acpi_uid" = "3" + register "acpi_uid" = "2" register "acpi_name" = ""VCM0"" - register "chip_name" = ""DW AF DAC"" + register "chip_name" = ""DW9714 VCM "" register "device_type" = "INTEL_ACPI_CAMERA_VCM"
- register "pr0" = ""\_SB.PCI0.I2C2.CAM0.PRIC"" register "vcm_compat" = ""dongwoon,dw9714""
+ register "has_power_resource" = "1" + #Controls + register "gpio_panel.gpio[0].gpio_num" = "GPP_F18" # EN_PP2800_AVDD + + #_ON + register "on_seq.ops_cnt" = "1" + register "on_seq.ops[0]" = "SEQ_OPS_GPIO_ENABLE(0, 5)" + + #_OFF + register "off_seq.ops_cnt" = "1" + register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + device i2c 0C on end end chip drivers/intel/mipi_camera - register "acpi_hid" = "ACPI_DT_NAMESPACE_HID" register "acpi_uid" = "1" register "acpi_name" = ""NVM0"" - register "chip_name" = ""GT24C08"" + register "chip_name" = ""GT24P64E"" register "device_type" = "INTEL_ACPI_CAMERA_NVM"
- register "pr0" = ""\_SB.PCI0.I2C2.CAM0.PRIC"" - register "nvm_size" = "0x2000" register "nvm_pagesize" = "1" register "nvm_readonly" = "1" register "nvm_width" = "0x10" - register "nvm_compat" = ""atmel,24c08"" + register "nvm_compat" = ""atmel,24c64""
device i2c 50 on end end