Edward O'Callaghan (eocallaghan@alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5758
-gerrit
commit c2168d2e6685444b6fda36480d6b26165257d385 Author: Edward O'Callaghan eocallaghan@alterapraxis.com Date: Thu May 15 21:13:33 2014 +1000
vendorcode/amd/agesa/*/gcc-intrin.h: Invaild inline asm
The 'm' (a memory reference) constraint makes little sense here since we are talking about a fs relative read, rather 'ir' (immediate or register) constraint is more sensible.
Line wrap these extraneously long lines found with these particular functions.
N.B. The 'p' constraint allows anything which fits the form of an address calculation where the 'ir' constraint is just a register /xor/ immediate. Hence would produce better code here however, unfortunately, clang does not currently support it properly.
Change-Id: Iaf3ad65791640e1060a2029e7ebb043f57b338a9 Signed-off-by: Edward O'Callaghan eocallaghan@alterapraxis.com --- src/vendorcode/amd/agesa/f14/Include/gcc-intrin.h | 60 +++++++++++++++-------- 1 file changed, 39 insertions(+), 21 deletions(-)
diff --git a/src/vendorcode/amd/agesa/f14/Include/gcc-intrin.h b/src/vendorcode/amd/agesa/f14/Include/gcc-intrin.h index 5ce3ee3..310223f 100644 --- a/src/vendorcode/amd/agesa/f14/Include/gcc-intrin.h +++ b/src/vendorcode/amd/agesa/f14/Include/gcc-intrin.h @@ -1,7 +1,7 @@ /* - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * + * Copyright (c) 2011, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2014, Edward O'Callaghan eocallaghan@alterapraxis.com + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright @@ -9,10 +9,10 @@ * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. - * + * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -23,9 +23,9 @@ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * */ - + #if defined (__GNUC__)
/* I/O intrin functions. */ @@ -526,39 +526,57 @@ static __inline__ __attribute__((always_inline)) void __lidt(void *Source) __asm__ __volatile__("lidt %0" : : "m"(*(short*)Source)); }
-static __inline__ __attribute__((always_inline)) void __writefsbyte(const unsigned long Offset, const unsigned char Data) +static __inline__ __attribute__((always_inline)) void +__writefsbyte(const unsigned long Offset, const unsigned char Data) { - __asm__("movb %b[Data], %%fs:%a[Offset]" : : [Offset] "ir" (Offset), [Data] "iq" (Data)); + __asm__ ("movb %b[Data], %%fs:%a[Offset]" + : + : [Offset] "ir" (Offset), [Data] "iq" (Data)); }
-static __inline__ __attribute__((always_inline)) void __writefsword(const unsigned long Offset, const unsigned short Data) +static __inline__ __attribute__((always_inline)) void +__writefsword(const unsigned long Offset, const unsigned short Data) { - __asm__("movw %w[Data], %%fs:%a[Offset]" : : [Offset] "ir" (Offset), [Data] "iq" (Data)); + __asm__ ("movw %w[Data], %%fs:%a[Offset]" + : + : [Offset] "ir" (Offset), [Data] "iq" (Data)); }
-static __inline__ __attribute__((always_inline)) void __writefsdword(const unsigned long Offset, const unsigned long Data) +static __inline__ __attribute__((always_inline)) void +__writefsdword(const unsigned long Offset, const unsigned long Data) { - __asm__("movl %k[Data], %%fs:%a[Offset]" : : [Offset] "ir" (Offset), [Data] "iq" (Data)); + __asm__ ("movl %[Data], %%fs:%a[Offset]" + : + : [Offset] "ir" (Offset), [Data] "iq" (Data)); }
-static __inline__ __attribute__((always_inline)) unsigned char __readfsbyte(const unsigned long Offset) +static __inline__ __attribute__((always_inline)) unsigned char +__readfsbyte(const unsigned long Offset) { unsigned char value; - __asm__("movb %%fs:%a[Offset], %b[value]" : [value] "=q" (value) : [Offset] "irm" (Offset)); + __asm__ ("movb %%fs:%a[Offset], %b[value]" + : [value] "=r" (value) + : [Offset] "ir" (Offset)); return value; }
-static __inline__ __attribute__((always_inline)) unsigned short __readfsword(const unsigned long Offset) +static __inline__ __attribute__((always_inline)) unsigned short +__readfsword(const unsigned long Offset) { unsigned short value; - __asm__("movw %%fs:%a[Offset], %w[value]" : [value] "=q" (value) : [Offset] "irm" (Offset)); + __asm__ ("movw %%fs:%a[Offset], %[value]" + : [value] "=r" (value) + : [Offset] "ir" (Offset)); return value; }
-static __inline__ __attribute__((always_inline)) unsigned long long __readfsdword(unsigned long long Offset) +static __inline__ __attribute__((always_inline)) unsigned long long +__readfsdword(unsigned long long Offset) { unsigned long long value; - __asm__("movl %%fs:%a[Offset], %k[value]" : [value] "=q" (value) : [Offset] "irm" (Offset)); + __asm__ ("movl %%fs:%a[Offset], %[value]" + : [value] "=r" (value) + : [Offset] "ir" (Offset)); return value; }
@@ -594,7 +612,7 @@ static __inline __attribute__(( __always_inline__)) void _mm_sfence (void) { __builtin_ia32_sfence (); } -#endif +#endif /* __SSE3__ */
static __inline__ __attribute__((always_inline)) void __stosb(unsigned char *dest, unsigned char data, size_t count) {