[coreboot-gerrit] Change in coreboot[master]: mb/google/volteer: use new tigerlake memory config

[Nick Vaccaro (Code Review)]

Hello Srinidhi N Kaushik, Wonkyu Kim, caveh jalali, build bot (Jenkins), Furquan Shaikh, Martin Roth, Patrick Georgi,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38715

to look at the new patch set (#11).

Change subject: mb/google/volteer: use new tigerlake memory config
......................................................................

mb/google/volteer: use new tigerlake memory config

Some of the common memory code that was being performed in
mainboard has moved into the soc to reduce redundant code.
This change adapts volteer to use tigerlake's new common code.

Define GPIO_MEM_CH_SEL to use for determining if all of memory
is populated or only half.

- if value read from GPIO_MEM_CH_SEL is 1, only half of DRAM is
    populated

- if value read is 0, or GPIO_MEM_CH_SEL is not defined, all of
    DRAM is populated

BUG=b:145642089, b:145238504, b:145564831
BRANCH=none
TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot
volteer, log into kernel, "cat /proc/meminfo" and verify it reports
"MemTotal:        8038196 kB".

Change-Id: I32c9b8a040728d44565806eece6cf60b6b6073b6
Signed-off-by: Nick Vaccaro 
---
M src/mainboard/google/volteer/Makefile.inc
A src/mainboard/google/volteer/romstage.c
M src/mainboard/google/volteer/variants/baseboard/Makefile.inc
M src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h
A src/mainboard/google/volteer/variants/baseboard/memory.c
5 files changed, 97 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/38715/11