Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35108 )
Change subject: soc/skylake: do not rely on P2SB data to generate DRHD ......................................................................
Patch Set 2:
(3 comments)
https://review.coreboot.org/c/coreboot/+/35108/2/src/soc/intel/skylake/chip_... File src/soc/intel/skylake/chip_fsp20.c:
https://review.coreboot.org/c/coreboot/+/35108/2/src/soc/intel/skylake/chip_... PS2, Line 487: // We set that in coreboot already : params->PchIoApicBdfValid = 0; if we set it in coreboot already, then why are we setting it to zero here for FSP?
https://review.coreboot.org/c/coreboot/+/35108/2/src/soc/intel/skylake/inclu... File src/soc/intel/skylake/include/soc/systemagent.h:
https://review.coreboot.org/c/coreboot/+/35108/2/src/soc/intel/skylake/inclu... PS2, Line 65: Hardcoded default values for PCI Bus:Dev.Fun for IOAPIC and HPET source?
https://review.coreboot.org/c/coreboot/+/35108/2/src/soc/intel/skylake/romst... File src/soc/intel/skylake/romstage/romstage_fsp20.c:
https://review.coreboot.org/c/coreboot/+/35108/2/src/soc/intel/skylake/romst... PS2, Line 291: // We set that in coreboot already : m_cfg->PchHpetBdfValid = 0; same as before. and why is this set in both romstage and ramstage?