3 comments:
File src/soc/intel/skylake/chip_fsp20.c:
// We set that in coreboot already
params->PchIoApicBdfValid = 0;
if we set it in coreboot already, then why are we setting it to zero here for FSP?
File src/soc/intel/skylake/include/soc/systemagent.h:
Patch Set #2, Line 65: Hardcoded default values for PCI Bus:Dev.Fun for IOAPIC and HPET
source?
File src/soc/intel/skylake/romstage/romstage_fsp20.c:
// We set that in coreboot already
m_cfg->PchHpetBdfValid = 0;
same as before. and why is this set in both romstage and ramstage?
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