[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/cannonlake: Set correct serirq mode based on SERIRQ_CONTINU...

[Jeremy Soller (Code Review)]

Jeremy Soller has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31536

Change subject: soc/intel/cannonlake: Set correct serirq mode based on SERIRQ_CONTINUOUS_MODE
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soc/intel/cannonlake: Set correct serirq mode based on SERIRQ_CONTINUOUS_MODE

Change-Id: I9ad4f5a6c7391fc6e813ec1306c708f449a69f59
---
M src/soc/intel/cannonlake/Kconfig
M src/soc/intel/cannonlake/fsp_params.c
2 files changed, 13 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/31536/1

diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index cd8819d..3716640 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -172,6 +172,13 @@
    default 24 if SOC_INTEL_CANNONLAKE_PCH_H
    default 16

+config SERIRQ_CONTINUOUS_MODE
+	bool
+	default n
+	help
+	  If you set this option to y, the serial IRQ machine will be
+	  operated in continuous mode.
+
 config SMM_TSEG_SIZE
    hex
    default 0x800000
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index c276c86..c95a68f 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -246,6 +246,12 @@

/* Set TccActivationOffset */
    tconfig->TccActivationOffset = config->tcc_offset;
+
+	/* Set correct Sirq mode based on config */
+	if (IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE))
+		params->PchSirqMode = 1;
+	else
+		params->PchSirqMode = 0;
 }

/* Mainboard GPIO Configuration */