build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42620 )
Change subject: broadwell: Align with haswell ......................................................................
Patch Set 8:
(12 comments)
https://review.coreboot.org/c/coreboot/+/42620/8/src/northbridge/intel/broad... File src/northbridge/intel/broadwell/northbridge.c:
https://review.coreboot.org/c/coreboot/+/42620/8/src/northbridge/intel/broad... PS8, Line 225: for (i = 0; i < NUM_MAP_ENTRIES; i++) { braces {} are not necessary for single statement blocks
https://review.coreboot.org/c/coreboot/+/42620/8/src/southbridge/intel/wildc... File src/southbridge/intel/wildcatpoint/lpc.c:
https://review.coreboot.org/c/coreboot/+/42620/8/src/southbridge/intel/wildc... PS8, Line 41: * Set miscellanous static southbridge features. 'miscellanous' may be misspelled - perhaps 'miscellaneous'?
https://review.coreboot.org/c/coreboot/+/42620/8/src/southbridge/intel/wildc... PS8, Line 132: case 1: /* INTA# */ int_line = config->pirqa_routing; break; trailing statements should be on next line
https://review.coreboot.org/c/coreboot/+/42620/8/src/southbridge/intel/wildc... PS8, Line 133: case 2: /* INTB# */ int_line = config->pirqb_routing; break; trailing statements should be on next line
https://review.coreboot.org/c/coreboot/+/42620/8/src/southbridge/intel/wildc... PS8, Line 134: case 3: /* INTC# */ int_line = config->pirqc_routing; break; trailing statements should be on next line
https://review.coreboot.org/c/coreboot/+/42620/8/src/southbridge/intel/wildc... PS8, Line 135: case 4: /* INTD# */ int_line = config->pirqd_routing; break; trailing statements should be on next line
https://review.coreboot.org/c/coreboot/+/42620/8/src/southbridge/intel/wildc... File src/southbridge/intel/wildcatpoint/me_status.c:
https://review.coreboot.org/c/coreboot/+/42620/8/src/southbridge/intel/wildc... PS8, Line 109: [ME_HFS2_STATE_BUP_VSCC_ERR] = "Error reading/matching the VSCC table in the descriptor", line over 96 characters
https://review.coreboot.org/c/coreboot/+/42620/8/src/southbridge/intel/wildc... PS8, Line 112: [ME_HFS2_STATE_BUP_MANUF_OVRD_STRAP] = "Possibly handle BUP manufacturing override strap", line over 96 characters
https://review.coreboot.org/c/coreboot/+/42620/8/src/southbridge/intel/wildc... PS8, Line 117: [ME_HFS2_STATE_BUP_CPU_RESET_DID_TIMEOUT_MEM_MISSING] = "Host error - CPU reset timeout, DID timeout, memory missing", line over 96 characters
https://review.coreboot.org/c/coreboot/+/42620/8/src/southbridge/intel/wildc... PS8, Line 147: [ME_HFS2_STATE_POLICY_FPB_ERR] = "Flash Partition Boundary is outside address space", line over 96 characters
https://review.coreboot.org/c/coreboot/+/42620/8/src/southbridge/intel/wildc... PS8, Line 148: [ME_HFS2_STATE_POLICY_DESCRIPTOR_ERR] = "ME cannot access the chipset descriptor region", line over 96 characters
https://review.coreboot.org/c/coreboot/+/42620/8/src/southbridge/intel/wildc... PS8, Line 149: [ME_HFS2_STATE_POLICY_VSCC_NO_MATCH] = "Required VSCC values for flash parts do not match", line over 96 characters