[coreboot-gerrit] Change in coreboot[master]: sb/intel/lynxpoint/pcie: Fix clock gating routine

[Angel Pons (Code Review)]

Hello build bot (Jenkins), Nico Huber, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/45713

to look at the new patch set (#3).

Change subject: sb/intel/lynxpoint/pcie: Fix clock gating routine
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sb/intel/lynxpoint/pcie: Fix clock gating routine

The use of `1 < 5` as a bit mask was obviously a typo. Correct it as
`1 << 5` to match what Intel doc #493816 (Lynx Point PCH BWG) states.

Change-Id: I85734a68a42ec65b124d68514039a1dda7946adc
Signed-off-by: Angel Pons 
---
M src/southbridge/intel/lynxpoint/pcie.c
1 file changed, 1 insertion(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/45713/3