Attention is currently required from: Chris Wang. Hello Chris Wang,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/50240
to review the following change.
Change subject: [WIP] soc/amd/picasso: add UPD for USB3 phy setting adjsut ......................................................................
[WIP] soc/amd/picasso: add UPD for USB3 phy setting adjsut
add UPD for USB3 phy setting adjust
Usb 3.1 PHY Parameters: 1. RX_EQ_DELTA_IQ_OVRD_VAL- Override value for rx_eq_delta_iq. Range 0-0xF 2. RX_EQ_DELTA_IQ_OVRD_EN - Enable override value for rx_eq_delta_iq. Range 0-0x1 3. Override value for rx_vref_ctrl. Range 0 - 0x1F 4. Enable override value for rx_vref_ctrl. Range 0 - 0x1 5. Override value for tx_vboost_lvl: 0 - 0x7. 6. Enable override value for tx_vboost_lvl. Range: 0 - 0x1 7. Override value for rx_vref_ctrl. Range 0 - 0x1F 8. Enable override value for rx_vref_ctrl. Range 0 - 0x1 9. Override value for tx_vboost_lvl: 0 - 0x7. 10. Enable override value for tx_vboost_lvl. Range: 0 - 0x1
BUG=b:175192931 TEST=Build
Change-Id: I1d5f69e840952cc5171af1ce8597628d1bede5cb Signed-off-by: Chris Wang chris.wang@amd.corp-partner.google.com --- M src/soc/amd/picasso/chip.h M src/soc/amd/picasso/fsp_params.c M src/vendorcode/amd/fsp/picasso/FspsUpd.h 3 files changed, 80 insertions(+), 21 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/50240/1
diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index 244d783..ca2c672 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -65,7 +65,14 @@ uint32_t rfmux_config; };
-#define USB_PORT_COUNT 6 +#define USB_PORT_COUNT 6 + +struct __packed usb3_phy_tune { + uint8_t rx_eq_delta_iq_ovrd_val; + uint8_t rx_eq_delta_iq_ovrd_en; +}; + +#define USB3_PORT_COUNT 4 #define USB_PD_PORT_COUNT 2
enum sd_emmc_driver_strength { @@ -247,6 +254,30 @@ USB_OC_NONE = 0xf, } usb_port_overcurrent_pin[USB_PORT_COUNT];
+ /* Usb 3.1 PHY Parameters */ + uint8_t usb3_phy_en; + /* + * 1,RX_EQ_DELTA_IQ_OVRD_VAL- Override value for rx_eq_delta_iq. Range 0-0xF + * 2,RX_EQ_DELTA_IQ_OVRD_EN - Enable override value for rx_eq_delta_iq. Range 0-0x1 + */ + struct usb3_phy_tune usb3_phy_tune_params[USB3_PORT_COUNT]; + /* Override value for rx_vref_ctrl. Range 0 - 0x1F */ + uint8_t usb3_rx_vref_ctrl; + /* Enable override value for rx_vref_ctrl. Range 0 - 0x1 */ + uint8_t usb3_rx_vref_ctrl_en; + /* Override value for tx_vboost_lvl: 0 - 0x7. */ + uint8_t usb_3_tx_vboost_lvl; + /* Enable override value for tx_vboost_lvl. Range: 0 - 0x1 */ + uint8_t usb_3_tx_vboost_lvl_en; + /* Override value for rx_vref_ctrl. Range 0 - 0x1F.*/ + uint8_t usb_3_rx_vref_ctrl_x; + /* Enable override value for rx_vref_ctrl. Range 0 - 0x1. */ + uint8_t usb_3_rx_vref_ctrl_en_x; + /* Override value for tx_vboost_lvl: 0 - 0x7. */ + uint8_t usb_3_tx_vboost_lvl_x; + /* Enable override value for tx_vboost_lvl. Range: 0 - 0x1. */ + uint8_t usb_3_tx_vboost_lvl_en_x; + /* The array index is the general purpose PCIe clock output number. */ enum gpp_clk_req_setting gpp_clk_config[GPP_CLK_OUTPUT_COUNT]; /* If using an external 48MHz OSC for codec, will disable internal X48M_OSC */ diff --git a/src/soc/amd/picasso/fsp_params.c b/src/soc/amd/picasso/fsp_params.c index 731a564..cd0208f 100644 --- a/src/soc/amd/picasso/fsp_params.c +++ b/src/soc/amd/picasso/fsp_params.c @@ -126,6 +126,25 @@ scfg->xhci_oc_pin_select |= (cfg->usb_port_overcurrent_pin[i] & 0xf) << (i * 4); } + + if (cfg->usb3_phy_en) { + memcpy (&scfg->usb_3_port0_phy_tune, &cfg->usb3_phy_tune_params[0], + izeof(scfg->usb_3_port0_phy_tune[0])); + memcpy (&scfg->usb_3_port1_phy_tune, &cfg->usb3_phy_tune_params[1], + izeof(scfg->usb_3_port0_phy_tune[1])); + memcpy (&scfg->usb_3_port2_phy_tune, &cfg->usb3_phy_tune_params[2], + izeof(scfg->usb_3_port0_phy_tune[2])); + memcpy (&scfg->usb_3_port3_phy_tune, &cfg->usb3_phy_tune_params[3], + izeof(scfg->usb_3_port0_phy_tune[3])); + scfg->usb_3_rx_vref_ctrl = cfg->usb3_rx_vref_ctrl; + scfg->usb_3_rx_vref_ctrl_en = cfg->usb3_rx_vref_ctrl_en; + scfg->usb_3_tx_vboost_lvl = cfg->usb_3_tx_vboost_lvl; + scfg->usb_3_tx_vboost_lvl_en = cfg->usb_3_tx_vboost_lvl_en; + scfg->usb_3_rx_vref_ctrl_x = cfg->usb_3_rx_vref_ctrl_x; + scfg->usb_3_rx_vref_ctrl_en_x = cfg->usb_3_rx_vref_ctrl_en_x; + scfg->usb_3_tx_vboost_lvl_x = cfg->usb_3_tx_vboost_lvl_x; + scfg->usb_3_tx_vboost_lvl_en_x = cfg->usb_3_tx_vboost_lvl_en_x; + } }
static void fsp_assign_ioapic_upds(FSP_S_CONFIG *scfg) diff --git a/src/vendorcode/amd/fsp/picasso/FspsUpd.h b/src/vendorcode/amd/fsp/picasso/FspsUpd.h index ee516f8..35758c2 100644 --- a/src/vendorcode/amd/fsp/picasso/FspsUpd.h +++ b/src/vendorcode/amd/fsp/picasso/FspsUpd.h @@ -39,26 +39,35 @@ /** Offset 0x0124**/ uint32_t gnb_ioapic_base; /** Offset 0x0128**/ uint8_t gnb_ioapic_id; /** Offset 0x0129**/ uint8_t fch_ioapic_id; - /** Offset 0x012A**/ uint8_t UnusedUpdSpace0[6]; - /** Offset 0x0130**/ uint8_t unused4; - /** Offset 0x0131**/ uint8_t DpPhyOverride; - /** Offset 0x0132**/ uint16_t EDpPhySel; - /** Offset 0x0134**/ uint8_t EDpVersion; - /** Offset 0x0135**/ uint8_t EDpTableSize; - /** Offset 0x0136**/ uint8_t DpVsPemphLevel; - /** Offset 0x0137**/ uint16_t MarginDeemPh; - /** Offset 0x0139**/ uint8_t Deemph6db4; - /** Offset 0x013A**/ uint8_t BoostAdj; - /** Offset 0x013B**/ uint16_t backlight_pwmhz; - /** Offset 0x013D**/ uint8_t pwron_digon_to_de; - /** Offset 0x013E**/ uint8_t pwron_de_to_varybl; - /** Offset 0x013F**/ uint8_t pwrdown_varybloff_to_de; - /** Offset 0x0140**/ uint8_t pwrdown_de_to_digoff; - /** Offset 0x0141**/ uint8_t pwroff_delay; - /** Offset 0x0142**/ uint8_t pwron_varybl_to_blon; - /** Offset 0x0143**/ uint8_t pwrdown_bloff_to_varybloff; - /** Offset 0x0144**/ uint8_t min_allowed_bl_level; - /** Offset 0x0145**/ uint8_t UnusedUpdSpace1[11]; + /** Offset 0x012A**/ uint16_t edp_phy_override; + /** Offset 0x012C**/ uint8_t edp_physel; + /** Offset 0x012D**/ uint8_t edp_dp_vs_pemph_level; + /** Offset 0x012E**/ uint16_t edp_margin_deemph; + /** Offset 0x0130**/ uint8_t edp_deemph_6db_4; + /** Offset 0x0131**/ uint8_t edp_boost_adj; + /** Offset 0x0132**/ uint16_t backlight_pwmhz; + /** Offset 0x0134**/ uint8_t pwron_digon_to_de; + /** Offset 0x0135**/ uint8_t pwron_de_to_varybl; + /** Offset 0x0136**/ uint8_t pwrdown_varybloff_to_de; + /** Offset 0x0137**/ uint8_t pwrdown_de_to_digoff; + /** Offset 0x0138**/ uint8_t pwroff_delay; + /** Offset 0x0139**/ uint8_t pwron_varybl_to_blon; + /** Offset 0x013A**/ uint8_t pwrdown_bloff_to_varybloff; + /** Offset 0x013B**/ uint8_t min_allowed_bl_level; + /** Offset 0x013C**/ uint8_t usb_3_phy_enable; + /** Offset 0x013D**/ uint8_t usb_3_port0_phy_tune[2]; + /** Offset 0x013F**/ uint8_t usb_3_port1_phy_tune[2]; + /** Offset 0x0141**/ uint8_t usb_3_port2_phy_tune[2]; + /** Offset 0x0143**/ uint8_t usb_3_port3_phy_tune[2]; + /** Offset 0x0145**/ uint8_t usb_3_rx_vref_ctrl; + /** Offset 0x0146**/ uint8_t usb_3_rx_vref_ctrl_en; + /** Offset 0x0147**/ uint8_t usb_3_tx_vboost_lvl; + /** Offset 0x0148**/ uint8_t usb_3_tx_vboost_lvl_en; + /** Offset 0x0149**/ uint8_t usb_3_rx_vref_ctrl_x; + /** Offset 0x014A**/ uint8_t usb_3_rx_vref_ctrl_en_x; + /** Offset 0x014B**/ uint8_t usb_3_tx_vboost_lvl_x; + /** Offset 0x014C**/ uint8_t usb_3_tx_vboost_lvl_en_x; + /** Offset 0x014D**/ uint8_t UnusedUpdSpace0[3]; /** Offset 0x0150**/ uint16_t UpdTerminator; } FSP_S_CONFIG;