[coreboot-gerrit] Change in coreboot[master]: enable JSL USB3 dbc

[Kane Chen (Code Review)]

Kane Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44407 )

Change subject: enable JSL USB3 dbc
......................................................................

enable JSL USB3 dbc

Signed-off-by: Kane Chen 
Change-Id: I2c6d84270431049947800d6598d596010414795e
---
M src/soc/intel/jasperlake/romstage/fsp_params.c
1 file changed, 1 insertion(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/44407/1

diff --git a/src/soc/intel/jasperlake/romstage/fsp_params.c b/src/soc/intel/jasperlake/romstage/fsp_params.c
index 809ae80..0639408 100644
--- a/src/soc/intel/jasperlake/romstage/fsp_params.c
+++ b/src/soc/intel/jasperlake/romstage/fsp_params.c
@@ -123,6 +123,7 @@
    soc_memory_init_params(m_cfg, config);

mainboard_memory_init_params(mupd);
+	m_cfg->PlatformDebugConsent = 3;
 }

__weak void mainboard_memory_init_params(FSPM_UPD *mupd)