Leroy P Leahy (leroy.p.leahy@intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13447
-gerrit
commit 2eb858855e58ef195666d7da5bc9641421913759 Author: Lee Leahy leroy.p.leahy@intel.com Date: Thu Jan 28 15:51:32 2016 -0800
soc/intel/quark: FSP MemoryInit Support
Add a dummy fill_power_state routine so that execution is able to reach FSP MemoryInit.
Testing: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Add "select DISPLAY_HOBS" * Add "select CONFIG_DISPLAY_UPD_DATA" * Add "select HAVE_FSP_PDAT_FILE" * Add "select HAVE_FSP_RAW_BIN" * Add "select HAVE_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Testing is successful if: * MemoryInit returns 0 (success) and * The the message "ERROR - Coreboot's requirements not met by FSP binary!" is not displayed
TEST=Build and run on Galileo
Change-Id: I2a116e1e769ac09915638aa9e5d7c58a4aac3cce Signed-off-by: Lee Leahy leroy.p.leahy@intel.com --- src/soc/intel/quark/romstage/Makefile.inc | 1 + src/soc/intel/quark/romstage/cache_as_ram.inc | 11 ++++++++-- src/soc/intel/quark/romstage/romstage.c | 30 +++++++++++++++++++++++++++ 3 files changed, 40 insertions(+), 2 deletions(-)
diff --git a/src/soc/intel/quark/romstage/Makefile.inc b/src/soc/intel/quark/romstage/Makefile.inc index 518c6a5..6ade32d 100644 --- a/src/soc/intel/quark/romstage/Makefile.inc +++ b/src/soc/intel/quark/romstage/Makefile.inc @@ -16,4 +16,5 @@ cpu_incs-y += $(src)/soc/intel/quark/romstage/esram_init.inc cpu_incs-y += $(src)/soc/intel/quark/romstage/cache_as_ram.inc
+romstage-y += romstage.c romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c diff --git a/src/soc/intel/quark/romstage/cache_as_ram.inc b/src/soc/intel/quark/romstage/cache_as_ram.inc index e1dcb62..e7aab3f 100644 --- a/src/soc/intel/quark/romstage/cache_as_ram.inc +++ b/src/soc/intel/quark/romstage/cache_as_ram.inc @@ -153,8 +153,15 @@ before_romstage:
/* Call cache_as_ram_main(struct cache_as_ram_params *) */ call cache_as_ram_main - movb $0xB8, %ah - jmp .Lhlt + +/* One will never return from cache_as_ram_main() in verstage so there's + * no such thing as after ram init. */ +#if !ENV_VERSTAGE +#include "src/drivers/intel/fsp1_1/after_raminit.S" +#endif + + movb $0x69, %ah + jmp .Lhlt
halt1: /* diff --git a/src/soc/intel/quark/romstage/romstage.c b/src/soc/intel/quark/romstage/romstage.c new file mode 100644 index 0000000..c1bc17e --- /dev/null +++ b/src/soc/intel/quark/romstage/romstage.c @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/early_variables.h> +#include <console/console.h> +#include <soc/pm.h> + +static struct chipset_power_state power_state CAR_GLOBAL; + +struct chipset_power_state *fill_power_state(void) +{ + struct chipset_power_state *ps = car_get_var_ptr(&power_state); + + ps->prev_sleep_state = 0; + printk(BIOS_DEBUG, "prev_sleep_state %d\n", ps->prev_sleep_state); + return ps; +}