Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46617 )
Change subject: device/pci_device: Map big PCI bars above 4 GiB ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46617/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/46617/1//COMMIT_MSG@10 PS1, Line 10: FIXME: This should probably go into the resource allocator.
I don't think the resource allocator is the right place to implement this policy. […]
Tests showed that this change indeed places the big BAR above 4GiB and the resource allocator no more complains about insufficent space, but booting using tianocore as payload fails.
The prefmem PCI bridge window covers both, prefmem BARs below 4GiB and prefmem BARs above 4 GiB, which is wrong. So this definitely needs support in the resource allocator that must place all prefmem BARs behind a bridge in one continuous MMIO region. In case there are 32bit BARs or BARs which must have an address below 4GiB, the allocator must bail out.
In this case it's an external GPU and mainboard code cannot make any assuptions about the devices plugged in.
Instead of having an error prone lookup table of devices that needs a BAR below 4GiB it's time to move to x86_64 in coreboot and deprecate 32bit OS as well.