[coreboot-gerrit] Change in ...coreboot[master]: sb/i82801gx: Don't rewrite over BCTRL

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32699 )

Change subject: sb/i82801gx: Don't rewrite over BCTRL
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sb/i82801gx: Don't rewrite over BCTRL

PCI_MIN_GNT is defined at offset 0x3e in <pci_def.h> which does not
apply to this PCI bridge because it is only defined for
"Header type 0 (normal devices)" (line 82).

BCTRL registry for D30:F0 is defined at offset 0x3e for i82801gx
(see ICH7 Family Datasheet page 355).
The write on that register is already done some lines above.
So remove wrong register name and the wrong code line.

Change-Id: Ib8a0514200f424049503bb8e4bc076ee6ae86ce3
Signed-off-by: Elyes HAOUAS 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32699
Tested-by: build bot (Jenkins) 
Reviewed-by: Nico Huber 
---
M src/southbridge/intel/i82801gx/pci.c
1 file changed, 0 insertions(+), 3 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Nico Huber: Looks good to me, approved

diff --git a/src/southbridge/intel/i82801gx/pci.c b/src/southbridge/intel/i82801gx/pci.c
index c54769f..22c5165 100644
--- a/src/southbridge/intel/i82801gx/pci.c
+++ b/src/southbridge/intel/i82801gx/pci.c
@@ -46,9 +46,6 @@
    reg8 |= (0x04 << 3);
    pci_write_config8(dev, SMLT, reg8);

-	/* Will this improve throughput of bus masters? */
-	pci_write_config8(dev, PCI_MIN_GNT, 0x06);
-
    /* Clear errors in status registers */
    reg16 = pci_read_config16(dev, PSTS);
    //reg16 |= 0xf900;