Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48745 )
Change subject: soc/intel/baytrail: add LPEA resources to southcluster.asl ......................................................................
soc/intel/baytrail: add LPEA resources to southcluster.asl
The LPEA device memory resources, required by Windows drivers, were not being set. Allocate required resources using soc/intel/braswell/acpi/southcluster.asl as a reference.
This patch alone is not sufficient for working audio under Windows on Baytrail ChromeOS devices, but it is a necessary component.
Test: boot Windows 10 on google/swanky, observe LPEA device working properly.
Change-Id: I7994d9b2c6e134c01b05cd7c61d309b6ba6e88e5 Signed-off-by: Matt DeVillier matt.devillier@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/48745 Reviewed-by: Angel Pons th3fanbus@gmail.com Reviewed-by: Patrick Rudolph siro@das-labor.org Reviewed-by: Paul Menzel paulepanter@users.sourceforge.net Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/baytrail/acpi/southcluster.asl 1 file changed, 28 insertions(+), 5 deletions(-)
Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Patrick Rudolph: Looks good to me, but someone else must approve Angel Pons: Looks good to me, approved
diff --git a/src/soc/intel/baytrail/acpi/southcluster.asl b/src/soc/intel/baytrail/acpi/southcluster.asl index f59f240..05d6b0d 100644 --- a/src/soc/intel/baytrail/acpi/southcluster.asl +++ b/src/soc/intel/baytrail/acpi/southcluster.asl @@ -136,11 +136,17 @@ 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, 0x00010000,,, FSEG)
- // PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS) + // LPEA Memory Region (0x20000000-0x201FFFFF) DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000,,, PMEM) + 0x00000000,,, LMEM) + + // PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS) + DwordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000,,, PMEM)
// TPM Area (0xfed40000-0xfed44fff) DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, @@ -152,10 +158,27 @@ Method (_CRS, 0, Serialized) {
+ /* Update LPEA resource area */ + CreateDWordField (MCRS, ^LMEM._MIN, LMIN) + CreateDWordField (MCRS, ^LMEM._MAX, LMAX) + CreateDWordField (MCRS, ^LMEM._LEN, LLEN) + If (LAnd (LNotEqual (LPFW, Zero), LEqual (LPEN, One))) + { + Store (LPFW, LMIN) + Store (0x00100000, LLEN) + Subtract (Add (LMIN, LLEN), One, LMAX) + } + Else + { + Store (Zero, LMIN) + Store (Zero, LMAX) + Store (Zero, LLEN) + } + /* Update PCI resource area */ - CreateDwordField(MCRS, ^PMEM._MIN, PMIN) - CreateDwordField(MCRS, ^PMEM._MAX, PMAX) - CreateDwordField(MCRS, ^PMEM._LEN, PLEN) + CreateDWordField (MCRS, ^PMEM._MIN, PMIN) + CreateDWordField (MCRS, ^PMEM._MAX, PMAX) + CreateDWordField (MCRS, ^PMEM._LEN, PLEN)
/* TOLM is BMBOUND accessible from IOSF so is saved in NVS */ Store (\TOLM, PMIN)