Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40110 )
Change subject: soc/intel/xeon_sp/cpx: add chip operation and PCIe enumeration ......................................................................
Patch Set 18:
(3 comments)
Thanks for the review. We are planning for the next phase of work on this aspect. Some further requirement/design discussions are on-going; a RFC will be sent to the community once the ideas are more concrete, then we will work on implementation.
https://review.coreboot.org/c/coreboot/+/40110/15/src/soc/intel/xeon_sp/cpx/... File src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h:
https://review.coreboot.org/c/coreboot/+/40110/15/src/soc/intel/xeon_sp/cpx/... PS15, Line 19: MAX_SOCKET * MAX_LOGIC_IIO_STAC
They are provided at src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds. […]
Done
https://review.coreboot.org/c/coreboot/+/40110/15/src/soc/intel/xeon_sp/cpx/... PS15, Line 22: uint8_t
yes, this is the same case for console.h as well.
Done
https://review.coreboot.org/c/coreboot/+/40110/15/src/soc/intel/xeon_sp/cpx/... File src/soc/intel/xeon_sp/cpx/soc_util.c:
https://review.coreboot.org/c/coreboot/+/40110/15/src/soc/intel/xeon_sp/cpx/... PS15, Line 34: MAX_IIO_STACK
MAX_IIO_STACK is the maximum number of IIO stacks per socket. […]
Done