Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38696 )
Change subject: vc/amd/fsp/picasso: Update UPD files ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38696/1/src/vendorcode/amd/fsp/pica... File src/vendorcode/amd/fsp/picasso/FspmUpd.h:
https://review.coreboot.org/c/coreboot/+/38696/1/src/vendorcode/amd/fsp/pica... PS1, Line 18:
From this comment, it looks like there was a newer version of FSP headers expected? I don't see any […]
Ah, didn't see this comment. I'm fine leaving the spaces for now. When ever the tool (which one?) is updated we can regenerate the file.
There was only 1 noticeable diff with coreboot-zork:
--- ../coreboot-zork/src/vendorcode/amd/fsp/picasso/FspmUpd.h 2020-03-20 10:28:23.736455600 -0600 +++ src/vendorcode/amd/fsp/picasso/FspmUpd.h 2020-04-28 15:45:39.390193949 -0600 @@ -55,7 +55,11 @@ /** Offset 0x00C2**/ uint8_t core_dldo_bypass; /** Offset 0x00C3**/ uint8_t min_soc_vid_offset; /** Offset 0x00C4**/ uint8_t aclk_dpm0_freq_400MHz; - /** Offset 0x00C5**/ uint8_t UnusedUpdSpace0[59]; + /** Offset 0x00C5**/ uint8_t reserved5; + /** Offset 0x00C6**/ uint8_t reserved6; + /** Offset 0x00C7**/ uint8_t reserved7; + /** Offset 0x00C8**/ uint32_t tseg_size; + /** Offset 0x00CC**/ uint8_t UnusedUpdSpace0[52]; /** Offset 0x0100**/ uint16_t Reserved100; /** Offset 0x0102**/ uint16_t UpdTerminator; } FSP_M_CONFIG;
I wasn't quite sure why this version has the tseg_size, but I decided to leave it. We can do more massaging as the FSP definition stabilizes. For now this is good enough to get it building and booting.