[coreboot-gerrit] [M] Change in coreboot[master]: WIP: arch/riscv: Enable FPU, vector extensions, timer and counters

[ron minnich (Code Review)]

ron minnich has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81128?usp=email )

Change subject: WIP: arch/riscv: Enable FPU, vector extensions, timer and counters
......................................................................

WIP: arch/riscv: Enable FPU, vector extensions, timer and counters

Enable on all harts, if available

Change-Id: I54be0467654ee7a445d61e4724dc58ee86b62d6f
---
M src/arch/riscv/include/arch/encoding.h
M src/arch/riscv/ramstage.S
M src/arch/riscv/virtual_memory.c
3 files changed, 39 insertions(+), 18 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/81128/1

diff --git a/src/arch/riscv/include/arch/encoding.h b/src/arch/riscv/include/arch/encoding.h
index 4f01e5c..b6a1b36 100644
--- a/src/arch/riscv/include/arch/encoding.h
+++ b/src/arch/riscv/include/arch/encoding.h
@@ -12,10 +12,11 @@
 #define MSTATUS_HPIE        0x00000040
 #define MSTATUS_MPIE        0x00000080
 #define MSTATUS_SPP         0x00000100
-#define MSTATUS_HPP         0x00000600
+#define MSTATUS_VS          0x00000600
 #define MSTATUS_MPP         0x00001800
 #define MSTATUS_FS          0x00006000
 #define MSTATUS_XS          0x00018000
+
 #define MSTATUS_MPRV        0x00020000
 #define MSTATUS_SUM         0x00040000
 #define MSTATUS_MXR         0x00080000
diff --git a/src/arch/riscv/ramstage.S b/src/arch/riscv/ramstage.S
index 954b155..693ef6c 100644
--- a/src/arch/riscv/ramstage.S
+++ b/src/arch/riscv/ramstage.S
@@ -35,8 +35,6 @@
    #NOTE a1 contains FDT and should not be cluttered above
    call hls_init

-	li   a0, CONFIG_RISCV_WORKING_HARTID
-	call smp_pause

# initialize entry of interrupt/exception
    la   t0, trap_entry
@@ -45,9 +43,16 @@
    # clear any pending interrupts
    csrwi mip, 0

-	call exit_car
    # set up the mstatus register
    call mstatus_init
+
+	# only continue with working hart, other harts will be resumed,
+	# when smp_resume is called, code below won't be executed on those
+	# harts
+	li   a0, CONFIG_RISCV_WORKING_HARTID
+	call smp_pause
+
+	call exit_car
    tail main

# These codes need to be implemented on a specific SoC
diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c
index 43e3d70..9f51618 100644
--- a/src/arch/riscv/virtual_memory.c
+++ b/src/arch/riscv/virtual_memory.c
@@ -13,23 +13,32 @@
  * to M-mode). In practice, this variable has been a lifesaver.  It is
  * still not quite determined which delegation might by unallowed by
  * the spec so for now we enumerate and set them all. */
-static int delegate = 0
-	| (1 << CAUSE_MISALIGNED_FETCH)
-	| (1 << CAUSE_FETCH_ACCESS)
-	| (1 << CAUSE_ILLEGAL_INSTRUCTION)
-	| (1 << CAUSE_BREAKPOINT)
-	| (1 << CAUSE_LOAD_ACCESS)
-	| (1 << CAUSE_STORE_ACCESS)
-	| (1 << CAUSE_USER_ECALL)
-	| (1 << CAUSE_FETCH_PAGE_FAULT)
-	| (1 << CAUSE_LOAD_PAGE_FAULT)
-	| (1 << CAUSE_STORE_PAGE_FAULT)
-	;
+static int delegate = 0 | (1 << CAUSE_MISALIGNED_FETCH) | (1 << CAUSE_FETCH_ACCESS) |
+		      (1 << CAUSE_ILLEGAL_INSTRUCTION) | (1 << CAUSE_BREAKPOINT) |
+		      (1 << CAUSE_LOAD_ACCESS) | (1 << CAUSE_STORE_ACCESS) |
+		      (1 << CAUSE_USER_ECALL) | (1 << CAUSE_FETCH_PAGE_FAULT) |
+		      (1 << CAUSE_LOAD_PAGE_FAULT) | (1 << CAUSE_STORE_PAGE_FAULT);

void mstatus_init(void)
 {
+	// initialize mstatus to defined value
+	uintptr_t mstatus_val = 0;
+
+	// enable FPU, if available
+	if (supports_extension('D') || supports_extension('F')) {
+		mstatus_val |= MSTATUS_FS;
+	}
+
+	// enable vector extensions
+	if (supports_extension('V')) {
+		mstatus_val |= MSTATUS_VS;
+	}
+
+	// update mstatus CSR
+	write_csr(mstatus, mstatus_val);
+
    // clear any pending timer interrupts.
-	clear_csr(mip,  MIP_STIP | MIP_SSIP);
+	clear_csr(mip, MIP_STIP | MIP_SSIP);

// enable machine and supervisor timer and
    // all other supervisor interrupts.
@@ -38,10 +47,16 @@
    // Delegate supervisor timer and other interrupts to supervisor mode,
    // if supervisor mode is supported.
    if (supports_extension('S')) {
-		set_csr(mideleg, MIP_STIP | MIP_SSIP);
+		set_csr(mideleg, MIP_STIP | MIP_SSIP | MIP_SEIP);
    	set_csr(medeleg, delegate);
    }

// Enable all user/supervisor-mode counters
    write_csr(mcounteren, 7);
+	write_csr(scounteren, 7);
+
+	// Enable FPU, if available
+	if (supports_extension('D') || supports_extension('F')) {
+		write_csr(fcsr, 0);
+	}
 }