[coreboot-gerrit] Change in coreboot[master]: soc/intel/ehl: Replace dt `HeciEnabled` by `CSE disable` config

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60727 )

Change subject: soc/intel/ehl: Replace dt `HeciEnabled` by `CSE disable` config
......................................................................

soc/intel/ehl: Replace dt `HeciEnabled` by `CSE disable` config

Lists of changes:

1. Drop `HeciEnabled` from dt and dt chip configuration.
2. Replace all logic that disables CSE based on the `HeciEnabled`
chip config with `DISABLE_CSE_AT_PRE_BOOT` config.

Mainboards that choose to make CSE enable during boot don't select
`cse disable` config.

Signed-off-by: Subrata Banik 
Change-Id: I76c625e6221fdef1343599e7dbc7739caa91bf98
---
M src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb
M src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
M src/soc/intel/elkhartlake/chip.h
M src/soc/intel/elkhartlake/smihandler.c
5 files changed, 1 insertion(+), 18 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/60727/1

diff --git a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb
index 1800541..0fdc88a 100644
--- a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb
+++ b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb
@@ -12,9 +12,6 @@
    register "pmc_gpe0_dw1" = "GPP_F"
    register "pmc_gpe0_dw2" = "GPP_E"

-	# Enable heci1 communication
-	register "HeciEnabled" = "1"
-
    # FSP configuration
    register "SaGv" = "SaGv_Enabled"
    register "SmbusEnable" = "1"
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
index 228bf60..87b455f 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
@@ -12,9 +12,6 @@
    register "pmc_gpe0_dw1" = "GPP_F"
    register "pmc_gpe0_dw2" = "GPP_E"

-	# Enable heci1 communication
-	register "HeciEnabled" = "1"
-
    # FSP configuration
    register "SaGv" = "SaGv_Disabled"
    register "SmbusEnable" = "1"
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
index ca90557..acb9286 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb
@@ -12,9 +12,6 @@
    register "pmc_gpe0_dw1" = "GPP_F"
    register "pmc_gpe0_dw2" = "GPP_E"

-	# Enable heci1 communication
-	register "HeciEnabled" = "1"
-
    # FSP configuration
    register "SaGv" = "SaGv_Disabled"
    register "SmbusEnable" = "1"
diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h
index e18e52d..210e92c 100644
--- a/src/soc/intel/elkhartlake/chip.h
+++ b/src/soc/intel/elkhartlake/chip.h
@@ -226,10 +226,6 @@

uint8_t Device4Enable;

-	/* HeciEnabled decides the state of Heci1 at end of boot
-	 * Setting to 0 (default) disables Heci1 and hides the device from OS */
-	uint8_t HeciEnabled;
-
    /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */
    uint8_t eist_enable;

diff --git a/src/soc/intel/elkhartlake/smihandler.c b/src/soc/intel/elkhartlake/smihandler.c
index 6637847..e86a770 100644
--- a/src/soc/intel/elkhartlake/smihandler.c
+++ b/src/soc/intel/elkhartlake/smihandler.c
@@ -16,11 +16,7 @@
  */
 void smihandler_soc_at_finalize(void)
 {
-	const struct soc_intel_elkhartlake_config *config;
-
-	config = config_of_soc();
-
-	if (!config->HeciEnabled && CONFIG(HECI_DISABLE_USING_SMM))
+	if (CONFIG(DISABLE_CSE_AT_PRE_BOOT) && CONFIG(HECI_DISABLE_USING_SMM))
    	heci_disable();
 }