[coreboot-gerrit] Change in coreboot[master]: soc/intel/xeon_sp: Use native CAR teardown

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48467 )

Change subject: soc/intel/xeon_sp: Use native CAR teardown
......................................................................

soc/intel/xeon_sp: Use native CAR teardown

This cleans up the postcar frame setup, which now gets used instead of
just going with TempRamExit MTRR's (Note that CPU init overwrites them
anyway).

TESTED on ocp/deltalake.

Change-Id: I756c2d479fef859a460696300422f08013a300f1
Signed-off-by: Arthur Heymans 
---
M src/soc/intel/xeon_sp/cpx/Kconfig
M src/soc/intel/xeon_sp/memmap.c
2 files changed, 22 insertions(+), 9 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/48467/1

diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig
index 369d474..ce92ed5 100644
--- a/src/soc/intel/xeon_sp/cpx/Kconfig
+++ b/src/soc/intel/xeon_sp/cpx/Kconfig
@@ -47,6 +47,14 @@
      says this needs to be 256KiB, but practice show this needs to
      be a lot more.

+config NO_FSP_TEMP_RAM_EXIT
+	bool
+	default y
+
+config INTEL_CAR_NEM
+	bool
+	default y
+
 config CPU_MICROCODE_CBFS_LOC
    hex
    default 0xfff0fdc0
diff --git a/src/soc/intel/xeon_sp/memmap.c b/src/soc/intel/xeon_sp/memmap.c
index cd81754..0af0ad2 100644
--- a/src/soc/intel/xeon_sp/memmap.c
+++ b/src/soc/intel/xeon_sp/memmap.c
@@ -29,17 +29,22 @@

void fill_postcar_frame(struct postcar_frame *pcf)
 {
-	/*
-	 * We need to make sure ramstage will be run cached. At this
-	 * point exact location of ramstage in cbmem is not known.
-	 * Instruct postcar to cache 16 megs under cbmem top which is
-	 * a safe bet to cover ramstage.
-	 */
-	uintptr_t top_of_ram = (uintptr_t)cbmem_top();
+	const uintptr_t top_of_ram = (uintptr_t)cbmem_top();
+	uintptr_t cbmem_base;
+	size_t cbmem_size;

+	/* Try account for the CBMEM region currently used and for future use */
+	cbmem_get_region((void **)&cbmem_base, &cbmem_size);
    printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram);
-	top_of_ram -= 16 * MiB;
-	postcar_frame_add_mtrr(pcf, top_of_ram, 16 * MiB, MTRR_TYPE_WRBACK);
+	printk(BIOS_DEBUG, "cbmem base_ptr: 0x%lx, size: 0x%lx\n", cbmem_base, cbmem_size);
+	/* Assume 4MiB will be enough for future cbmem objects (FSP-S, ramstage, ...) */
+	cbmem_base -= 4 * MiB;
+	cbmem_base = ALIGN_DOWN(cbmem_base, 4 * MiB);
+
+	/* Align the top to make sure we don't use too many MTRR's */
+	cbmem_size = ALIGN_UP(top_of_ram - cbmem_base, 4 * MiB);
+
+	postcar_frame_add_mtrr(pcf, cbmem_base, cbmem_size, MTRR_TYPE_WRBACK);
    /* Cache the TSEG region */
    if (CONFIG(TSEG_STAGE_CACHE))
    	postcar_enable_tseg_cache(pcf);