Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33190
Change subject: soc/intel/icelake: Replace PCI device LPC to ESPI as per EDS ......................................................................
soc/intel/icelake: Replace PCI device LPC to ESPI as per EDS
As per Icelake EDS PCI device B:D:F (0:0x1f:0) referred as ESPI, hence modify SoC code to reflect the same.
Change-Id: I4990ea6d9b7b4c0eac2b3eea559f5469f086e827 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/include/device/pci_ids.h M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/icelake/Makefile.inc M src/soc/intel/icelake/acpi.c R src/soc/intel/icelake/acpi/espi.asl M src/soc/intel/icelake/acpi/southbridge.asl M src/soc/intel/icelake/bootblock/pch.c M src/soc/intel/icelake/bootblock/report_platform.c M src/soc/intel/icelake/chip.c R src/soc/intel/icelake/espi.c R src/soc/intel/icelake/include/soc/espi.h M src/soc/intel/icelake/include/soc/pci_devs.h M src/soc/intel/icelake/pmutil.c M src/soc/intel/icelake/romstage/fsp_params.c 14 files changed, 60 insertions(+), 57 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/33190/1
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index a35e134..795e4c0 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2723,13 +2723,13 @@ #define PCI_DEVICE_ID_INTEL_CNL_Y_PREMIUM_LPC 0x9d83 #define PCI_DEVICE_ID_INTEL_CNP_H_LPC_Q370 0xa306 #define PCI_DEVICE_ID_INTEL_CNP_H_LPC_QM370 0xa30c -#define PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_LPC 0x3480 -#define PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_LPC_REV0 0x3481 -#define PCI_DEVICE_ID_INTEL_ICL_U_PREMIUM_LPC 0x3482 -#define PCI_DEVICE_ID_INTEL_ICL_BASE_Y_LPC 0x3483 -#define PCI_DEVICE_ID_INTEL_ICL_BASE_U_LPC 0x3484 -#define PCI_DEVICE_ID_INTEL_ICL_Y_PREMIUM_LPC 0x3487 -#define PCI_DEVICE_ID_INTEL_ICL_SUPER_Y_LPC 0x3486 +#define PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_ESPI 0x3480 +#define PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_ESPI_REV0 0x3481 +#define PCI_DEVICE_ID_INTEL_ICL_U_PREMIUM_ESPI 0x3482 +#define PCI_DEVICE_ID_INTEL_ICL_BASE_Y_ESPI 0x3483 +#define PCI_DEVICE_ID_INTEL_ICL_BASE_U_ESPI 0x3484 +#define PCI_DEVICE_ID_INTEL_ICL_Y_PREMIUM_ESPI 0x3487 +#define PCI_DEVICE_ID_INTEL_ICL_SUPER_Y_ESPI 0x3486 #define PCI_DEVICE_ID_INTEL_CMP_SUPER_U_LPC 0x0281 #define PCI_DEVICE_ID_INTEL_CMP_PREMIUM_Y_LPC 0x0283 #define PCI_DEVICE_ID_INTEL_CMP_PREMIUM_U_LPC 0x0284 diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c index 86547a4..7e78bf9 100644 --- a/src/soc/intel/common/block/lpc/lpc.c +++ b/src/soc/intel/common/block/lpc/lpc.c @@ -156,13 +156,13 @@ PCI_DEVICE_ID_INTEL_CNL_Y_PREMIUM_LPC, PCI_DEVICE_ID_INTEL_CNP_H_LPC_Q370, PCI_DEVICE_ID_INTEL_CNP_H_LPC_QM370, - PCI_DEVICE_ID_INTEL_ICL_BASE_U_LPC, - PCI_DEVICE_ID_INTEL_ICL_BASE_Y_LPC, - PCI_DEVICE_ID_INTEL_ICL_U_PREMIUM_LPC, - PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_LPC, - PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_LPC_REV0, - PCI_DEVICE_ID_INTEL_ICL_SUPER_Y_LPC, - PCI_DEVICE_ID_INTEL_ICL_Y_PREMIUM_LPC, + PCI_DEVICE_ID_INTEL_ICL_BASE_U_ESPI, + PCI_DEVICE_ID_INTEL_ICL_BASE_Y_ESPI, + PCI_DEVICE_ID_INTEL_ICL_U_PREMIUM_ESPI, + PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_ESPI, + PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_ESPI_REV0, + PCI_DEVICE_ID_INTEL_ICL_SUPER_Y_ESPI, + PCI_DEVICE_ID_INTEL_ICL_Y_PREMIUM_ESPI, PCI_DEVICE_ID_INTEL_CMP_SUPER_U_LPC, PCI_DEVICE_ID_INTEL_CMP_PREMIUM_Y_LPC, PCI_DEVICE_ID_INTEL_CMP_PREMIUM_U_LPC, diff --git a/src/soc/intel/icelake/Makefile.inc b/src/soc/intel/icelake/Makefile.inc index cd6a6ba..0d4e32d 100644 --- a/src/soc/intel/icelake/Makefile.inc +++ b/src/soc/intel/icelake/Makefile.inc @@ -13,19 +13,19 @@ bootblock-y += bootblock/pch.c bootblock-y += pmutil.c bootblock-y += bootblock/report_platform.c +bootblock-y += espi.c bootblock-y += gpio.c bootblock-y += gspi.c bootblock-y += i2c.c bootblock-y += memmap.c bootblock-y += spi.c -bootblock-y += lpc.c bootblock-y += p2sb.c bootblock-y += uart.c
+romstage-y += espi.c romstage-y += gpio.c romstage-y += gspi.c romstage-y += i2c.c -romstage-y += lpc.c romstage-y += memmap.c romstage-y += pmutil.c romstage-y += reset.c @@ -36,6 +36,7 @@ ramstage-y += chip.c ramstage-y += cpu.c ramstage-y += elog.c +ramstage-y += espi.c ramstage-y += finalize.c ramstage-y += fsp_params.c ramstage-y += gpio.c @@ -44,7 +45,6 @@ ramstage-y += gpio.c ramstage-y += i2c.c ramstage-y += lockdown.c -ramstage-y += lpc.c ramstage-y += memmap.c ramstage-y += p2sb.c ramstage-y += pmc.c diff --git a/src/soc/intel/icelake/acpi.c b/src/soc/intel/icelake/acpi.c index f16469e..4dbd17e 100644 --- a/src/soc/intel/icelake/acpi.c +++ b/src/soc/intel/icelake/acpi.c @@ -169,7 +169,7 @@ void soc_fill_fadt(acpi_fadt_t *fadt) { const uint16_t pmbase = ACPI_BASE_ADDRESS; - const struct device *dev = PCH_DEV_LPC; + const struct device *dev = PCH_DEV_ESPI; const struct soc_intel_icelake_config *config = dev->chip_info;
if (!config->PmTimerDisabled) { @@ -194,7 +194,7 @@
void acpi_create_gnvs(struct global_nvs_t *gnvs) { - const struct device *dev = PCH_DEV_LPC; + const struct device *dev = PCH_DEV_ESPI; const struct soc_intel_icelake_config *config = dev->chip_info;
/* Set unknown wake source */ diff --git a/src/soc/intel/icelake/acpi/lpc.asl b/src/soc/intel/icelake/acpi/espi.asl similarity index 96% rename from src/soc/intel/icelake/acpi/lpc.asl rename to src/soc/intel/icelake/acpi/espi.asl index f936392..4456812 100644 --- a/src/soc/intel/icelake/acpi/lpc.asl +++ b/src/soc/intel/icelake/acpi/espi.asl @@ -13,10 +13,12 @@ * GNU General Public License for more details. */
+ +/* Device identifier is not changed to ESPI to maintain coherency with ec.asl */ Device (LPCB) { Name (_ADR, 0x001f0000) - Name (_DDN, "LPC Bus Device") + Name (_DDN, "ESPI Bus Device")
Device (FWH) { diff --git a/src/soc/intel/icelake/acpi/southbridge.asl b/src/soc/intel/icelake/acpi/southbridge.asl index 1b9abe6..ffd2fcc 100644 --- a/src/soc/intel/icelake/acpi/southbridge.asl +++ b/src/soc/intel/icelake/acpi/southbridge.asl @@ -32,8 +32,8 @@ /* GPIO controller */ #include "gpio.asl"
-/* LPC 0:1f.0 */ -#include "lpc.asl" +/* ESPI 0:1f.0 */ +#include "espi.asl"
/* PCH HDA */ #include "pch_hda.asl" diff --git a/src/soc/intel/icelake/bootblock/pch.c b/src/soc/intel/icelake/bootblock/pch.c index 0940791..60ab006 100644 --- a/src/soc/intel/icelake/bootblock/pch.c +++ b/src/soc/intel/icelake/bootblock/pch.c @@ -26,8 +26,8 @@ #include <intelblocks/smbus.h> #include <intelblocks/tco.h> #include <soc/bootblock.h> +#include <soc/espi.h> #include <soc/iomap.h> -#include <soc/lpc.h> #include <soc/p2sb.h> #include <soc/pch.h> #include <soc/pci_devs.h> diff --git a/src/soc/intel/icelake/bootblock/report_platform.c b/src/soc/intel/icelake/bootblock/report_platform.c index e7c010e..314a7b1 100644 --- a/src/soc/intel/icelake/bootblock/report_platform.c +++ b/src/soc/intel/icelake/bootblock/report_platform.c @@ -49,13 +49,13 @@ u16 lpcid; const char *name; } pch_table[] = { - { PCI_DEVICE_ID_INTEL_ICL_BASE_U_LPC, "Icelake-U Base" }, - { PCI_DEVICE_ID_INTEL_ICL_BASE_Y_LPC, "Icelake-Y Base" }, - { PCI_DEVICE_ID_INTEL_ICL_U_PREMIUM_LPC, "Icelake-U Premium" }, - { PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_LPC, "Icelake-U Super" }, - { PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_LPC_REV0, "Icelake-U Super REV0" }, - { PCI_DEVICE_ID_INTEL_ICL_SUPER_Y_LPC, "Icelake-Y Super" }, - { PCI_DEVICE_ID_INTEL_ICL_Y_PREMIUM_LPC, "Icelake-Y Premium" }, + { PCI_DEVICE_ID_INTEL_ICL_BASE_U_ESPI, "Icelake-U Base" }, + { PCI_DEVICE_ID_INTEL_ICL_BASE_Y_ESPI, "Icelake-Y Base" }, + { PCI_DEVICE_ID_INTEL_ICL_U_PREMIUM_ESPI, "Icelake-U Premium" }, + { PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_ESPI, "Icelake-U Super" }, + { PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_ESPI_REV0, "Icelake-U Super REV0" }, + { PCI_DEVICE_ID_INTEL_ICL_SUPER_Y_ESPI, "Icelake-Y Super" }, + { PCI_DEVICE_ID_INTEL_ICL_Y_PREMIUM_ESPI, "Icelake-Y Premium" }, };
static struct { @@ -170,7 +170,7 @@ static void report_pch_info(void) { int i; - pci_devfn_t dev = PCH_DEV_LPC; + pci_devfn_t dev = PCH_DEV_ESPI; uint16_t lpcid = get_dev_id(dev); const char *pch_type = "Unknown";
diff --git a/src/soc/intel/icelake/chip.c b/src/soc/intel/icelake/chip.c index 2616db1..eff1c7a 100644 --- a/src/soc/intel/icelake/chip.c +++ b/src/soc/intel/icelake/chip.c @@ -89,7 +89,8 @@ case PCH_DEVFN_GSPI2: return "SPI2"; case PCH_DEVFN_EMMC: return "EMMC"; case PCH_DEVFN_SDCARD: return "SDXC"; - case PCH_DEVFN_LPC: return "LPCB"; + /* Keeping ACPI device name coherent with ec.asl */ + case PCH_DEVFN_ESPI: return "LPCB"; case PCH_DEVFN_P2SB: return "P2SB"; case PCH_DEVFN_PMC: return "PMC_"; case PCH_DEVFN_HDA: return "HDAS"; diff --git a/src/soc/intel/icelake/lpc.c b/src/soc/intel/icelake/espi.c similarity index 99% rename from src/soc/intel/icelake/lpc.c rename to src/soc/intel/icelake/espi.c index 3d05824..cca185c 100644 --- a/src/soc/intel/icelake/lpc.c +++ b/src/soc/intel/icelake/espi.c @@ -24,9 +24,9 @@ #include <intelblocks/lpc_lib.h> #include <intelblocks/pcr.h> #include <reg_script.h> +#include <soc/espi.h> #include <soc/iomap.h> #include <soc/irq.h> -#include <soc/lpc.h> #include <soc/pci_devs.h> #include <soc/pcr_ids.h>
diff --git a/src/soc/intel/icelake/include/soc/lpc.h b/src/soc/intel/icelake/include/soc/espi.h similarity index 93% rename from src/soc/intel/icelake/include/soc/lpc.h rename to src/soc/intel/icelake/include/soc/espi.h index ebfcaa8..9308433 100644 --- a/src/soc/intel/icelake/include/soc/lpc.h +++ b/src/soc/intel/icelake/include/soc/espi.h @@ -13,12 +13,10 @@ * GNU General Public License for more details. */
-#ifndef _SOC_ICELAKE_LPC_H_ -#define _SOC_ICELAKE_LPC_H_ +#ifndef _SOC_ICELAKE_ESPI_H_ +#define _SOC_ICELAKE_ESPI_H_
-#include <stdint.h> - -/* PCI Configuration Space (D31:F0): LPC */ +/* PCI Configuration Space (D31:F0): ESPI */ #define SCI_IRQ_SEL (7 << 0) #define SCIS_IRQ9 0 #define SCIS_IRQ10 1 diff --git a/src/soc/intel/icelake/include/soc/pci_devs.h b/src/soc/intel/icelake/include/soc/pci_devs.h index 3cb06172..889b5c5 100644 --- a/src/soc/intel/icelake/include/soc/pci_devs.h +++ b/src/soc/intel/icelake/include/soc/pci_devs.h @@ -171,22 +171,24 @@ #define PCH_DEV_GSPI0 _PCH_DEV(SIO3, 2) #define PCH_DEV_GSPI1 _PCH_DEV(SIO3, 3)
-#define PCH_DEV_SLOT_LPC 0x1f -#define PCH_DEVFN_LPC _PCH_DEVFN(LPC, 0) -#define PCH_DEVFN_P2SB _PCH_DEVFN(LPC, 1) -#define PCH_DEVFN_PMC _PCH_DEVFN(LPC, 2) -#define PCH_DEVFN_HDA _PCH_DEVFN(LPC, 3) -#define PCH_DEVFN_SMBUS _PCH_DEVFN(LPC, 4) -#define PCH_DEVFN_SPI _PCH_DEVFN(LPC, 5) -#define PCH_DEVFN_GBE _PCH_DEVFN(LPC, 6) -#define PCH_DEVFN_TRACEHUB _PCH_DEVFN(LPC, 7) -#define PCH_DEV_LPC _PCH_DEV(LPC, 0) -#define PCH_DEV_P2SB _PCH_DEV(LPC, 1) -#define PCH_DEV_PMC _PCH_DEV(LPC, 2) -#define PCH_DEV_HDA _PCH_DEV(LPC, 3) -#define PCH_DEV_SMBUS _PCH_DEV(LPC, 4) -#define PCH_DEV_SPI _PCH_DEV(LPC, 5) -#define PCH_DEV_GBE _PCH_DEV(LPC, 6) -#define PCH_DEV_TRACEHUB _PCH_DEV(LPC, 7) +#define PCH_DEV_SLOT_ESPI 0x1f +#define PCH_DEV_SLOT_LPC PCH_DEV_SLOT_ESPI +#define PCH_DEVFN_ESPI _PCH_DEVFN(ESPI, 0) +#define PCH_DEVFN_P2SB _PCH_DEVFN(ESPI, 1) +#define PCH_DEVFN_PMC _PCH_DEVFN(ESPI, 2) +#define PCH_DEVFN_HDA _PCH_DEVFN(ESPI, 3) +#define PCH_DEVFN_SMBUS _PCH_DEVFN(ESPI, 4) +#define PCH_DEVFN_SPI _PCH_DEVFN(ESPI, 5) +#define PCH_DEVFN_GBE _PCH_DEVFN(ESPI, 6) +#define PCH_DEVFN_TRACEHUB _PCH_DEVFN(ESPI, 7) +#define PCH_DEV_ESPI _PCH_DEV(ESPI, 0) +#define PCH_DEV_LPC PCH_DEV_ESPI +#define PCH_DEV_P2SB _PCH_DEV(ESPI, 1) +#define PCH_DEV_PMC _PCH_DEV(ESPI, 2) +#define PCH_DEV_HDA _PCH_DEV(ESPI, 3) +#define PCH_DEV_SMBUS _PCH_DEV(ESPI, 4) +#define PCH_DEV_SPI _PCH_DEV(ESPI, 5) +#define PCH_DEV_GBE _PCH_DEV(ESPI, 6) +#define PCH_DEV_TRACEHUB _PCH_DEV(ESPI, 7)
#endif diff --git a/src/soc/intel/icelake/pmutil.c b/src/soc/intel/icelake/pmutil.c index 1c47783..cdb39ad 100644 --- a/src/soc/intel/icelake/pmutil.c +++ b/src/soc/intel/icelake/pmutil.c @@ -30,10 +30,10 @@ #include <intelblocks/rtc.h> #include <intelblocks/tco.h> #include <stdlib.h> +#include <soc/espi.h> #include <soc/gpe.h> #include <soc/gpio.h> #include <soc/iomap.h> -#include <soc/lpc.h> #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/smbus.h> diff --git a/src/soc/intel/icelake/romstage/fsp_params.c b/src/soc/intel/icelake/romstage/fsp_params.c index 86788a5..ba06803 100644 --- a/src/soc/intel/icelake/romstage/fsp_params.c +++ b/src/soc/intel/icelake/romstage/fsp_params.c @@ -66,7 +66,7 @@
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { - const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC); + const struct device *dev = dev_find_slot(0, PCH_DEVFN_ESPI); assert(dev != NULL); const config_t *config = dev->chip_info; FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;