[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Update FSP UPDs to turn on USB4/TBT

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38737 )

Change subject: soc/intel/tigerlake: Update FSP UPDs to turn on USB4/TBT
......................................................................

soc/intel/tigerlake: Update FSP UPDs to turn on USB4/TBT

FSP needs to know to allow the root ports for USB4/TBT to be enabled
This patch may need additional checks for each board as it might not
be the right thing to turn them all on for every Tiger Lake board.

BUG=b:141609883
BRANCH=NONE
TEST=Built image and verified that the root ports were visible with lspci

Change-Id: I3f020e20fa8e9fd1ac69d883f4dc1fcbb330a3bf
Signed-off-by: Brandon Breitenstein 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38737
Tested-by: build bot (Jenkins) 
Reviewed-by: Tim Wawrzynczak 
---
M src/soc/intel/tigerlake/fsp_params_tgl.c
M src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
2 files changed, 32 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Tim Wawrzynczak: Looks good to me, approved

diff --git a/src/soc/intel/tigerlake/fsp_params_tgl.c b/src/soc/intel/tigerlake/fsp_params_tgl.c
index f3f700f..a8be407 100644
--- a/src/soc/intel/tigerlake/fsp_params_tgl.c
+++ b/src/soc/intel/tigerlake/fsp_params_tgl.c
@@ -186,6 +186,15 @@
    /* Enable Hybrid storage auto detection */
    params->HybridStorageMode = config->HybridStorageMode;

+	/* USB4/TBT */
+	for (i = 0; i < ARRAY_SIZE(params->ITbtPcieRootPortEn); i++) {
+		dev = pcidev_on_root(SA_DEV_SLOT_TBT, i);
+		if (dev)
+			params->ITbtPcieRootPortEn[i] = dev->enabled;
+		else
+			params->ITbtPcieRootPortEn[i] = 0;
+	}
+
    mainboard_silicon_init_params(params);
 }

diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
index e275e59..95f637e 100644
--- a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
+++ b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
@@ -120,6 +120,29 @@
    m_cfg->TcssXhciEn = config->TcssXhciEn;
    m_cfg->TcssXdciEn = config->TcssXdciEn;

+	/* USB4/TBT */
+	dev = pcidev_path_on_root(SA_DEVFN_TBT0);
+	if (dev)
+		m_cfg->TcssItbtPcie0En = dev->enabled;
+	else
+		m_cfg->TcssItbtPcie0En = 0;
+	dev = pcidev_path_on_root(SA_DEVFN_TBT1);
+	if (dev)
+		m_cfg->TcssItbtPcie1En = dev->enabled;
+	else
+		m_cfg->TcssItbtPcie1En = 0;
+
+	dev = pcidev_path_on_root(SA_DEVFN_TBT2);
+	if (dev)
+		m_cfg->TcssItbtPcie2En = dev->enabled;
+	else
+		m_cfg->TcssItbtPcie2En = 0;
+	dev = pcidev_path_on_root(SA_DEVFN_TBT3);
+	if (dev)
+		m_cfg->TcssItbtPcie3En = dev->enabled;
+	else
+		m_cfg->TcssItbtPcie3En = 0;
+
    /* Enable Hyper Threading */
    m_cfg->HyperThreading = 1;
    /* Disable Lock PCU Thermal Management registers */