[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/cannonlake: Add FSP SPI CS options

[Paul Fagerburg (Code Review)]

Paul Fagerburg has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32793 )

Change subject: soc/intel/cannonlake: Add FSP SPI CS options
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Patch Set 1:

(3 comments)

https://review.coreboot.org/#/c/32793/1/src/soc/intel/cannonlake/chip.h 
File src/soc/intel/cannonlake/chip.h:

https://review.coreboot.org/#/c/32793/1/src/soc/intel/cannonlake/chip.h@a407 
PS1, Line 407: 
Why were these removed in this CL? They seem unrelated.

https://review.coreboot.org/#/c/32793/1/src/soc/intel/cannonlake/chip.h@345 
PS1, Line 345: 	uint8_t SerialIoSpi0CsPolarity[2];
These should have #define constants instead of magic numbers.

https://review.coreboot.org/#/c/32793/1/src/soc/intel/cannonlake/fsp_params.... 
File src/soc/intel/cannonlake/fsp_params.c:

https://review.coreboot.org/#/c/32793/1/src/soc/intel/cannonlake/fsp_params.... 
PS1, Line 90: 	params->SerialIoSpi0CsPolarity[0] = config->SerialIoSpi0CsPolarity[0];
Once you have #define constants, you'll have to re-factor this into a loop, sorry.