Martin Roth (gaumless@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10886
-gerrit
commit 1d207852f4c03277b39ee014d7f6dd2534507440 Author: Martin Roth gaumless@gmail.com Date: Sat Jul 11 13:56:58 2015 -0600
Verify Kconfigs symbols are not zero for hex and int type symbols
For hex and int type kconfig symbols, IS_ENABLED() doesn't work. Instead check to make sure they're defined and not zero. In some cases, zero might be a valid value, but it didn't look like zero was valid in these cases.
Change-Id: Ib51fb31b3babffbf25ed3ae4ed11a2dc9a4be709 Signed-off-by: Martin Roth gaumless@gmail.com --- src/cpu/x86/mtrr/earlymtrr.c | 2 +- src/drivers/elog/boot_count.c | 4 ++-- src/include/cpu/x86/mtrr.h | 4 ++-- src/include/pc80/mc146818rtc.h | 4 ++-- src/southbridge/amd/agesa/hudson/acpi/fch.asl | 4 +--- 5 files changed, 8 insertions(+), 10 deletions(-)
diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c index 3db676b..9561d8d 100644 --- a/src/cpu/x86/mtrr/earlymtrr.c +++ b/src/cpu/x86/mtrr/earlymtrr.c @@ -50,7 +50,7 @@ static void do_early_mtrr_init(const unsigned long *mtrr_msrs) wrmsr(msr_nr, msr); }
-#if defined(CONFIG_XIP_ROM_SIZE) +#if defined(CONFIG_XIP_ROM_SIZE) && CONFIG_XIP_ROM_SIZE /* enable write through caching so we can do execute in place * on the flash rom. * Determine address by calculating the XIP_ROM_SIZE sized area with diff --git a/src/drivers/elog/boot_count.c b/src/drivers/elog/boot_count.c index 0b5c402..e853e36 100644 --- a/src/drivers/elog/boot_count.c +++ b/src/drivers/elog/boot_count.c @@ -34,10 +34,10 @@ # include "option_table.h" # define BOOT_COUNT_CMOS_OFFSET (CMOS_VSTART_boot_count_offset >> 3) #else -# if defined(CONFIG_ELOG_BOOT_COUNT_CMOS_OFFSET) +# if defined(CONFIG_ELOG_BOOT_COUNT_CMOS_OFFSET) && CONFIG_ELOG_BOOT_COUNT_CMOS_OFFSET # define BOOT_COUNT_CMOS_OFFSET CONFIG_ELOG_BOOT_COUNT_CMOS_OFFSET # else -# error "Must define CONFIG_ELOG_BOOT_COUNT_CMOS_OFFSET" +# error "Must configure CONFIG_ELOG_BOOT_COUNT_CMOS_OFFSET" # endif #endif
diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 86ce57b..bd0b603 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -87,8 +87,8 @@ void set_var_mtrr(unsigned reg, unsigned base, unsigned size, unsigned type); (x>>6)|(x>>7)|(x>>8)|((1<<18)-1)) #define _ALIGN_UP_POW2(x) ((x + _POW2_MASK(x)) & ~_POW2_MASK(x))
-#if !defined(CONFIG_RAMTOP) -# error "CONFIG_RAMTOP not defined" +#if !defined(CONFIG_RAMTOP) || !CONFIG_RAMTOP +# error "CONFIG_RAMTOP not configured" #endif
#if ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE -1)) != 0) diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h index c74af66..0e15273 100644 --- a/src/include/pc80/mc146818rtc.h +++ b/src/include/pc80/mc146818rtc.h @@ -186,10 +186,10 @@ unsigned read_option_lowlevel(unsigned start, unsigned size, unsigned def); # include "option_table.h" # define CMOS_POST_OFFSET (CMOS_VSTART_cmos_post_offset >> 3) #else -# if defined(CONFIG_CMOS_POST_OFFSET) +# if defined(CONFIG_CMOS_POST_OFFSET) && CONFIG_CMOS_POST_OFFSET # define CMOS_POST_OFFSET CONFIG_CMOS_POST_OFFSET # else -# error "Must define CONFIG_CMOS_POST_OFFSET" +# error "Must configure CONFIG_CMOS_POST_OFFSET" # endif #endif
diff --git a/src/southbridge/amd/agesa/hudson/acpi/fch.asl b/src/southbridge/amd/agesa/hudson/acpi/fch.asl index ce73894..6006e67 100644 --- a/src/southbridge/amd/agesa/hudson/acpi/fch.asl +++ b/src/southbridge/amd/agesa/hudson/acpi/fch.asl @@ -179,12 +179,10 @@ Method(_INI, 0) { /* Determine the OS we're running on */ OSFL()
-#ifdef CONFIG_HUDSON_IMC_FWM -#if CONFIG_HUDSON_IMC_FWM +#if defined(CONFIG_HUDSON_IMC_FWM) && CONFIG_HUDSON_IMC_FWM #include "acpi/AmdImc.asl" /* Hudson IMC function */ ITZE() /* enable IMC Fan Control*/ #endif -#endif } /* End Method(_SB._INI) */
Method(OSFL, 0){