Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36431 )
Change subject: soc/intel/icelake: Enable caching on SPI memory-mapped boot device unconditionally
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Patch Set 5: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/36431/5//COMMIT_MSG
Commit Message:
https://review.coreboot.org/c/coreboot/+/36431/5//COMMIT_MSG@14
PS5, Line 14: This assumption will not hold good for APL/GLK platform where boot
: from eMMC is also possible options.
This is sufficiently clear for the previous sentences.
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