[coreboot-gerrit] Change in coreboot[master]: nb/intel/gm45: Use new fixed BAR accessors

[Angel Pons (Code Review)]

Attention is currently required from: Patrick Rudolph.
Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/51880 )

Change subject: nb/intel/gm45: Use new fixed BAR accessors
......................................................................

nb/intel/gm45: Use new fixed BAR accessors

Tested with BUILD_TIMELESS=1, Roda RK9 remains identical.

Change-Id: I18f40d1bc3172b3c1b6b4828cefdb91aea679ba2
Signed-off-by: Angel Pons 
---
M src/northbridge/intel/gm45/early_reset.c
M src/northbridge/intel/gm45/gma.c
2 files changed, 9 insertions(+), 12 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/51880/1

diff --git a/src/northbridge/intel/gm45/early_reset.c b/src/northbridge/intel/gm45/early_reset.c
index 1783880..a4c9b94 100644
--- a/src/northbridge/intel/gm45/early_reset.c
+++ b/src/northbridge/intel/gm45/early_reset.c
@@ -12,8 +12,7 @@

/* Reset DRAM power-up settings in CLKCFG (they are not
       affected by system reset but may disrupt raminit). */
-	MCHBAR32(CLKCFG_MCHBAR) =
-		(MCHBAR32(CLKCFG_MCHBAR) & ~(3 << 21)) | (1 << 3);
+	mchbar_clrsetbits32(CLKCFG_MCHBAR, 3 << 21, 1 << 3);

/*\ Next settings are the real purpose of this function:
        If these steps are not performed, reset results in power off. */
@@ -21,9 +20,8 @@
    /* Initialize some DRAM settings to 1 populated rank of 128MB. */
    FOR_EACH_CHANNEL(ch) {
    	/* Configure DRAM control mode. */
-		MCHBAR32(CxDRC0_MCHBAR(ch)) =
-			(MCHBAR32(CxDRC0_MCHBAR(ch)) & ~CxDRC0_RANKEN_MASK) |
-			(ch ? 0 : CxDRC0_RANKEN(0));
+		mchbar_clrsetbits32(CxDRC0_MCHBAR(ch), CxDRC0_RANKEN_MASK,
+			(ch ? 0 : CxDRC0_RANKEN(0)));
    	MCHBAR32(CxDRC1_MCHBAR(ch)) =
    		(MCHBAR32(CxDRC1_MCHBAR(ch)) | CxDRC1_NOTPOP_MASK) &
    		~(ch ? 0 : CxDRC1_NOTPOP(0));
@@ -31,23 +29,22 @@
    		(MCHBAR32(CxDRC2_MCHBAR(ch)) | CxDRC2_NOTPOP_MASK) &
    		~(ch ? 0 : CxDRC2_NOTPOP(0));
    	/*if (timings && (timings->mem_clock == MEM_CLOCK_1067MT))
-			MCHBAR32(CxDRC2_MCHBAR(ch)) |= CxDRC2_CLK1067MT;*/
+			mchbar_setbits32(CxDRC2_MCHBAR(ch), CxDRC2_CLK1067MT);*/

/* Program rank boundaries (CxDRBy). */
    	for (r = 0; r < RANKS_PER_CHANNEL; r += 2)
-			MCHBAR32(CxDRBy_MCHBAR(ch, r)) =
-				CxDRBy_BOUND_MB(r, 128) |
-				CxDRBy_BOUND_MB(r+1, 128);
+			mchbar_write32(CxDRBy_MCHBAR(ch, r),
+				CxDRBy_BOUND_MB(r, 128) | CxDRBy_BOUND_MB(r + 1, 128));
    }
    /* Set DCC mode to no operation and do magic 0xf0 thing. */
-	MCHBAR32(DCC_MCHBAR) = (MCHBAR32(DCC_MCHBAR) & ~DCC_CMD_MASK) | DCC_CMD_NOP;
+	mchbar_clrsetbits32(DCC_MCHBAR, DCC_CMD_MASK, DCC_CMD_NOP);

pci_and_config8(PCI_DEV(0, 0, 0), 0xf0, ~(1 << 2));

pci_or_config8(PCI_DEV(0, 0, 0), 0xf0, (1 << 2));

/* Normally, we would set this after successful raminit. */
-	MCHBAR32(DCC_MCHBAR) |= (1 << 19);
+	mchbar_setbits32(DCC_MCHBAR, 1 << 19);

system_reset();
 }
diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c
index c771ea2..178149d 100644
--- a/src/northbridge/intel/gm45/gma.c
+++ b/src/northbridge/intel/gm45/gma.c
@@ -33,7 +33,7 @@
 {
    const u16 cdclk_sel = pci_read_config16(dev, GCFGC_OFFSET) & GCFGC_CD_MASK;

-	switch (MCHBAR8(HPLLVCO_MCHBAR) & 0x7) {
+	switch (mchbar_read8(HPLLVCO_MCHBAR) & 0x7) {
    case VCO_2666:
    case VCO_4000:
    case VCO_5333: