[coreboot-gerrit] [XS] Change in coreboot[main]: fatcat-ish: disable UART0 RX

[Subrata Banik (Code Review)]

Attention is currently required from: Bora Guvendik, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Li1 Feng, Pranava Y N.

Subrata Banik has posted comments on this change by Li1 Feng. ( https://review.coreboot.org/c/coreboot/+/86005?usp=email )

Change subject: fatcat-ish: disable UART0 RX
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Patch Set 3:

(2 comments)

File src/mainboard/google/fatcat/variants/fatcat/fw_config.c:

https://review.coreboot.org/c/coreboot/+/86005/comment/45a81031_aeebc5f5?usp... :
PS2, Line 421: 	/* GPP_D05:     NC */
             : 	PAD_NC(GPP_D05, NONE)
> I updated problem statement, it happens when ISH switches is OFF, might be FPS is ON, or both are OFF. So inside FPS doesn't cover all cases.

Ack

https://review.coreboot.org/c/coreboot/+/86005/comment/0eef90aa_10372809?usp... :
PS2, Line 432: 	/* GPP_D05:     ISH_UART0_RXD */
             : 	PAD_CFG_NF(GPP_D05, NONE, DEEP, NF2),
> We still have ISH log, just console doesn't accept input. With ISH PM enabled,  anyway console doesn't pick up input most of the time because it's in LPM; not much impact from what I experienced.

Can you please mention the same in the commit msg as well to ensure we know thar ISH console won't be able to receive a response w/ this CL.