[coreboot-gerrit] Change in coreboot[master]: mb/pcengines/apu1/mainboard.c: reorder includes

[Nico Huber (Code Review)]

Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42512 )

Change subject: mb/pcengines/apu1/mainboard.c: reorder includes
......................................................................

mb/pcengines/apu1/mainboard.c: reorder includes

Originally, there was problem with PC Engines apu1 platform
which returned serial number value as -64. It was caused by wrong
value of dev->bus->secondary.
Source of the problem is in Porting.h header file. It contains
'#pragma pack(1)' which affects struct device. As mainboard.c
uses different binary layout because of this attribute,
reference dev->bus->secondary lands at wrong memory address.
This patch reorder includes and put <AGESA.h> and <AMD.h>
at the end of list, making struct device consistent.
As a result bus number value in device's structure is correct
and hence serial number.

TEST=`dmidecode -t 2` command in Linux Debian

Signed-off-by: Piotr Kleinschmidt 
Change-Id: I5e8690d100b38ac7889395d375c0ff32bdefda0b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42512
Reviewed-by: Michał Żygowski 
Reviewed-by: Nico Huber 
Tested-by: build bot (Jenkins) 
---
M src/mainboard/pcengines/apu1/mainboard.c
1 file changed, 5 insertions(+), 4 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Nico Huber: Looks good to me, but someone else must approve
  Michał Żygowski: Looks good to me, approved

diff --git a/src/mainboard/pcengines/apu1/mainboard.c b/src/mainboard/pcengines/apu1/mainboard.c
index a2a78c5..45d326a 100644
--- a/src/mainboard/pcengines/apu1/mainboard.c
+++ b/src/mainboard/pcengines/apu1/mainboard.c
@@ -1,8 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

#include <amdblocks/acpimmio.h>
-#include <AGESA.h>
-#include <AMD.h>
+
 #include <console/console.h>
 #include <device/device.h>
 #include <device/mmio.h>
@@ -11,12 +10,14 @@
 #include <southbridge/amd/common/amd_pci_util.h>
 #include <smbios.h>
 #include <string.h>
-#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
 #include <southbridge/amd/cimx/sb800/pci_devs.h>
 #include <northbridge/amd/agesa/agesa_helper.h>
 #include <northbridge/amd/agesa/family14/pci_devs.h>
 #include <superio/nuvoton/nct5104d/nct5104d.h>
 #include "gpio_ftns.h"
+#include <AGESA.h>
+#include <AMD.h>
+#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>

/***********************************************************
  * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
@@ -301,7 +302,7 @@

/* Read in the last 3 bytes of NIC's MAC address. */
    bar18 = pci_read_config32(dev, 0x18);
-	bar18 &= 0xFFFFFC00;
+	bar18 &= 0xFFFFFFF0;
    for (i = 3; i < 6; i++) {
    	mac_addr <<= 8;
    	mac_addr |= read8((u8 *)bar18 + i);