[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Move GPIO PM configuration to soc level

[EricR Lai (Code Review)]

Hello Patrick Rudolph, Kane Chen, Mathew King, Duncan Laurie, Tim Wawrzynczak, build bot (Jenkins), Furquan Shaikh,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/37685

to look at the new patch set (#8).

Change subject: soc/intel/cannonlake: Move GPIO PM configuration to soc level
......................................................................

soc/intel/cannonlake: Move GPIO PM configuration to soc level

Enable/disable GPIO clock gating when enter/exit s0ix is common
request on CNL/CML. Move it from board level to soc level.

BUG=b:144002424
TEST=measure power consumption under s0ix

Signed-off-by: Eric Lai 
Change-Id: I120f8369b8d3cf7ac821332bdfa124f6ed0570e9
---
M src/soc/intel/cannonlake/acpi/gpio.asl
M src/soc/intel/cannonlake/acpi/lpit.asl
M src/soc/intel/common/acpi/platform.asl
3 files changed, 60 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/37685/8