[coreboot-gerrit] Change in coreboot[master]: arch/riscv: Add error detection for supports_extension

[Xiang Wang (Code Review)]

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37130 )

Change subject: arch/riscv: Add error detection for supports_extension
......................................................................

arch/riscv: Add error detection for supports_extension

Change-Id: I5df3d82b9a9b4968beea6040b86628b58fd8a45d
Signed-off-by: Xiang Wang 
---
M src/arch/riscv/include/arch/cpu.h
1 file changed, 8 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/37130/1

diff --git a/src/arch/riscv/include/arch/cpu.h b/src/arch/riscv/include/arch/cpu.h
index 72a8a69..dd70af7 100644
--- a/src/arch/riscv/include/arch/cpu.h
+++ b/src/arch/riscv/include/arch/cpu.h
@@ -49,7 +49,7 @@
  * */
 int soc_supports_extension(char ext);

-static inline int supports_extension(char ext)
+static inline int supports_extension_imp(char ext)
 {
    uintptr_t isa = read_csr(misa);
    if (isa)
@@ -58,6 +58,13 @@
    	return soc_supports_extension(ext);
 }

+#define supports_extension(c)\
+({\
+	_Static_assert(((c >= 'A') && (c <= 'Z')),\
+		"The parameter of supports_extension must be [A-Z]");\
+	supports_extension_imp(c);\
+})
+
 /* If the SOC does not implement misa, the read misa will be zero.
  * Such SOC requires a non-standard mechanism to detect machine XLEN.
  * If the soc does not implement misa, implement this function.