Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46418 )
Change subject: mb/intel/adlrvp: Fix SSD detection issue on ADL RVP
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Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46418/1/src/mainboard/intel/adlrvp/...
File src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/46418/1/src/mainboard/intel/adlrvp/...
PS1, Line 44: # Enable PCH PCIE RP 5 using CLK 2
: register "PcieRpEnable[4]" = "1"
: register "PcieClkSrcClkReq[2]" = "2"
: register "PcieClkSrcUsage[2]" = "0x4"
Alright, good to know. Thanks! […]
yes Angel, already Tim has answered your question, your understanding is perfect
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Gerrit-Project: coreboot
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Gerrit-Change-Id: I7e26429281f8d3b9edae0f266a5868118369be3f
Gerrit-Change-Number: 46418
Gerrit-PatchSet: 1
Gerrit-Owner: Subrata Banik
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Gerrit-Reviewer: Angel Pons
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