[coreboot-gerrit] [L] Change in coreboot[master]: mb/intel: Add 2 SPR sockets CRB Archer City

[Shelly Chang (Code Review)]

Attention is currently required from: Patrick Rudolph, Simon Chou, Johnny Lin, Paul Menzel, Shuming Chu (Shuming), Arthur Heymans, Lean Sheng Tan, Juan Sanchez.

Shelly Chang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71968 )

Change subject: mb/intel: Add 2 SPR sockets CRB Archer City
......................................................................

Patch Set 31:

(3 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/71968/comment/08aae3a9_45262e68 
PS29, Line 7: add Archer City CRB support
> Maybe mention the type: Add 2 SPR sockets CRB Archer City

Done

Patchset:

PS28:
> The multisocket support depends on Change-Id: Ie682bfa376d699c0eee8de0752cd6ae6d8d81fee

Done

File src/mainboard/intel/archercity_crb/romstage.c:

https://review.coreboot.org/c/coreboot/+/71968/comment/2c8ec3e7_e1d41f19 
PS27, Line 124: 	mupd->FspmConfig.serialDebugMsgLvl = 0x1;
> In our current design we use VPD to configure FSP log level as well under xeon_sp/spr: […]

Done