Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/20533
Change subject: soc/intel/cannonlake: Add memory map support ......................................................................
soc/intel/cannonlake: Add memory map support
Calculate the top of ram from output of Fsp reserved memory range.
Change-Id: I0dcc8f737c5811c9010cc4a20ea0126ab3f90f14 Signed-off-by: Lijian Zhao lijian.zhao@intel.com --- M src/soc/intel/cannonlake/Makefile.inc A src/soc/intel/cannonlake/memmap.c 2 files changed, 144 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/20533/1
diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 480e047..b0fe57f 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -12,11 +12,11 @@ bootblock-y += bootblock/report_platform.c bootblock-y += gpio.c
-romstage-y += cbmem.c +romstage-y += memmap.c romstage-y += reset.c romstage-$(CONFIG_DRIVERS_UART_8250MEM) += uart.c
-ramstage-y += cbmem.c +ramstage-y += memmap.c ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c ramstage-$(CONFIG_DRIVERS_UART_8250MEM) += uart.c
diff --git a/src/soc/intel/cannonlake/memmap.c b/src/soc/intel/cannonlake/memmap.c new file mode 100644 index 0000000..fb9d5f8 --- /dev/null +++ b/src/soc/intel/cannonlake/memmap.c @@ -0,0 +1,142 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015-2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <cbmem.h> +#include <device/device.h> +#include <device/pci.h> +#include <fsp/util.h> +#include <soc/msr.h> +#include <soc/systemagent.h> +#include <soc/pci_devs.h> +#include <stdlib.h> + +#ifdef __x86_64__ +#define CRx_IN "q" +#define CRx_RET "=q" +#else +#define CRx_IN "r" +#define CRx_RET "=r" +#endif +#define COMPILER_BARRIER "memory" + +static alwaysinline uint32_t read_xmm0(void) +{ + uint32_t value; + __asm__ __volatile__ ( + "movd %%xmm0, %0" + : CRx_RET(value) + : + : COMPILER_BARRIER + ); + return value; +} + +static alwaysinline void write_xmm0(uint32_t data) +{ + __asm__ __volatile__ ( + "movd %0, %%xmm0" + : + : CRx_IN(data) + : COMPILER_BARRIER + ); +} + +/* + * Host Memory Map: + * + * +--------------------------+ TOUUD + * | | + * +--------------------------+ 4GiB + * | PCI Address Space | + * +--------------------------+ TOLUD (also maps into MC address space) + * | iGD | + * +--------------------------+ BDSM + * | GTT | + * +--------------------------+ BGSM + * | TSEG | + * +--------------------------+ TSEGMB + * | DMA Protected Region | + * +--------------------------+ DPR + * | PRM (C6DRAM/SGX) | + * +--------------------------+ PRMRR + * | Trace Memory | + * +--------------------------+ top_of_ram + * | Reserved - FSP/CBMEM | + * +--------------------------+ TOLUM + * | Usage DRAM | + * +--------------------------+ 0 + * + * Some of the base registers above can be equal making the size of those + * regions 0. The reason is because the memory controller internally subtracts + * the base registers from each other to determine sizes of the regions. In + * other words, the memory map is in a fixed order no matter what. + */ + +u32 top_of_32bit_ram(void) +{ + u32 top_of_ram = 0; + struct range_entry fsp_mem; + u32 fsp_reserve_base; + int status; + + /* + * Check if Tseg has been initialized, we will use this as a flag + * to check if the MRC is done, and only then continue to read the + * FSP Reserve Memory HOB. + */ + status = fsp_find_reserved_memory(&fsp_mem); + if (status == 0) { + fsp_reserve_base = (u32)range_entry_base(&fsp_mem); + top_of_ram = ALIGN_UP((uintptr_t)fsp_reserve_base, 16*MiB); + write_xmm0(top_of_ram); + } else + top_of_ram = read_xmm0(); + + return top_of_ram; +} + +void *cbmem_top(void) +{ + /* + * +-------------------------+ Top of RAM (aligned) + * | System Management Mode | + * | code and data | Length: CONFIG_TSEG_SIZE + * | (TSEG) | + * +-------------------------+ SMM base (aligned) + * | | + * | Chipset Reserved Memory | + * | | + * +-------------------------+ top_of_ram (aligned) + * | | + * | CBMEM Root | + * | | + * +-------------------------+ + * | | + * | FSP Reserved Memory | + * | | + * +-------------------------+ + * | | + * | Various CBMEM Entries | + * | | + * +-------------------------+ top_of_stack (8 byte aligned) + * | | + * | stack (CBMEM Entry) | + * | | + * +-------------------------+ + */ + return (void *)top_of_32bit_ram(); +}