Xi Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44703 )
Change subject: soc/mediatek/mt8192: Do EMI init before dram calibration ......................................................................
Patch Set 37:
(4 comments)
https://review.coreboot.org/c/coreboot/+/44703/36/src/soc/mediatek/mt8192/em... File src/soc/mediatek/mt8192/emi.c:
https://review.coreboot.org/c/coreboot/+/44703/36/src/soc/mediatek/mt8192/em... PS36, Line 380: 0x1 << 0
0x1, or BIT(0)
Ack
https://review.coreboot.org/c/coreboot/+/44703/36/src/soc/mediatek/mt8192/em... PS36, Line 384: 0x1 << 0
0x1, or BIT(0)
Ack
https://review.coreboot.org/c/coreboot/+/44703/36/src/soc/mediatek/mt8192/em... PS36, Line 385: (read32(&ch[0].emi_chn.cona) & 0x1)
remove ()
Ack
https://review.coreboot.org/c/coreboot/+/44703/36/src/soc/mediatek/mt8192/em... PS36, Line 389: write32((u32 *)0x40000000, read32((u32 *)0x40000000)); : write32((u32 *)0x40000100, read32((u32 *)0x40000100)); : write32((u32 *)0x40000200, read32((u32 *)0x40000200)); : write32((u32 *)0x40000300, read32((u32 *)0x40000300)); :
can you explain what are we doing here?
0x40000000 is the base addr of DRAM, EMI does basic memory R/W to adjust emi HW setting.