4 comments:
File src/soc/mediatek/mt8192/emi.c:
Patch Set #36, Line 380: 0x1 << 0
0x1, or BIT(0)
Ack
Patch Set #36, Line 384: 0x1 << 0
0x1, or BIT(0)
Ack
Patch Set #36, Line 385: (read32(&ch[0].emi_chn.cona) & 0x1)
remove ()
Ack
write32((u32 *)0x40000000, read32((u32 *)0x40000000));
write32((u32 *)0x40000100, read32((u32 *)0x40000100));
write32((u32 *)0x40000200, read32((u32 *)0x40000200));
write32((u32 *)0x40000300, read32((u32 *)0x40000300));
can you explain what are we doing here?
0x40000000 is the base addr of DRAM, EMI does basic memory R/W to adjust emi HW setting.
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