Nico Huber has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32760 )
Change subject: soc/intel/broadwell: Clean up the bootflow ......................................................................
soc/intel/broadwell: Clean up the bootflow
Call the raminit from a common location instead of from the mainboard specific code.
Change-Id: I65d522237a0bb7b2c032536ede10e2cf93c134d8 Signed-off-by: Arthur Heymans arthur@aheymans.xyz Reviewed-on: https://review.coreboot.org/c/coreboot/+/32760 Reviewed-by: Nico Huber nico.h@gmx.de Reviewed-by: Matt DeVillier matt.devillier@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/auron/romstage.c M src/mainboard/google/jecht/romstage.c M src/mainboard/intel/wtm2/romstage.c M src/mainboard/purism/librem_bdw/romstage.c M src/soc/intel/broadwell/include/soc/romstage.h M src/soc/intel/broadwell/romstage/romstage.c 6 files changed, 46 insertions(+), 51 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Matt DeVillier: Looks good to me, but someone else must approve
diff --git a/src/mainboard/google/auron/romstage.c b/src/mainboard/google/auron/romstage.c index 4974899..568c4c8 100644 --- a/src/mainboard/google/auron/romstage.c +++ b/src/mainboard/google/auron/romstage.c @@ -27,17 +27,16 @@ { }
-void mainboard_romstage_entry(struct romstage_params *rp) +void mainboard_pre_raminit(struct romstage_params *rp) { - post_code(0x32); - /* Fill out PEI DATA */ mainboard_fill_pei_data(&rp->pei_data); mainboard_fill_spd_data(&rp->pei_data);
- /* Call into the real romstage main with this board's attributes. */ - romstage_common(rp); +}
+void mainboard_post_raminit(struct romstage_params *rp) +{ /* Do variant-specific init */ variant_romstage_entry(rp); } diff --git a/src/mainboard/google/jecht/romstage.c b/src/mainboard/google/jecht/romstage.c index 8d1ae8a..86888c8 100644 --- a/src/mainboard/google/jecht/romstage.c +++ b/src/mainboard/google/jecht/romstage.c @@ -27,17 +27,15 @@ #include "onboard.h"
-void mainboard_romstage_entry(struct romstage_params *rp) +void mainboard_pre_raminit(struct romstage_params *rp) { - post_code(0x32); - /* Fill out PEI DATA */ mainboard_fill_pei_data(&rp->pei_data); mainboard_fill_spd_data(&rp->pei_data); +}
- /* Call into the real romstage main with this board's attributes. */ - romstage_common(rp); - +void mainboard_post_raminit(struct romstage_params *rp) +{ if (CONFIG(CHROMEOS)) init_bootmode_straps(); } diff --git a/src/mainboard/intel/wtm2/romstage.c b/src/mainboard/intel/wtm2/romstage.c index 5b8df27..f4e3366 100644 --- a/src/mainboard/intel/wtm2/romstage.c +++ b/src/mainboard/intel/wtm2/romstage.c @@ -22,12 +22,12 @@ #include <soc/pei_wrapper.h> #include <soc/romstage.h>
-void mainboard_romstage_entry(struct romstage_params *rp) +void mainboard_pre_raminit(struct romstage_params *rp) { - post_code(0x32); - /* Fill out PEI DATA */ mainboard_fill_pei_data(&rp->pei_data); +}
- romstage_common(rp); +void mainboard_post_raminit(struct romstage_params *rp) +{ } diff --git a/src/mainboard/purism/librem_bdw/romstage.c b/src/mainboard/purism/librem_bdw/romstage.c index 5330d191..0e1ad88 100644 --- a/src/mainboard/purism/librem_bdw/romstage.c +++ b/src/mainboard/purism/librem_bdw/romstage.c @@ -18,11 +18,12 @@ #include <soc/pei_wrapper.h> #include <soc/romstage.h>
-void mainboard_romstage_entry(struct romstage_params *rp) +void mainboard_pre_raminit(struct romstage_params *rp) { /* Fill out PEI DATA */ mainboard_fill_pei_data(&rp->pei_data); +}
- /* Initialize memory */ - romstage_common(rp); +void mainboard_post_raminit(struct romstage_params *rp) +{ } diff --git a/src/soc/intel/broadwell/include/soc/romstage.h b/src/soc/intel/broadwell/include/soc/romstage.h index 46f29d6..d65692a 100644 --- a/src/soc/intel/broadwell/include/soc/romstage.h +++ b/src/soc/intel/broadwell/include/soc/romstage.h @@ -27,8 +27,8 @@ struct pei_data pei_data; };
-void mainboard_romstage_entry(struct romstage_params *params); -void romstage_common(struct romstage_params *params); +void mainboard_pre_raminit(struct romstage_params *params); +void mainboard_post_raminit(struct romstage_params *params);
void raminit(struct pei_data *pei_data);
diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index 2a3ac8b..acbca14 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -103,8 +103,34 @@ /* Initialize GPIOs */ init_gpios(mainboard_gpio_config);
- /* Call into mainboard. */ - mainboard_romstage_entry(&rp); + /* Fill in mainboard pei_date. */ + mainboard_pre_raminit(&rp); + + post_code(0x32); + + timestamp_add_now(TS_BEFORE_INITRAM); + + rp.pei_data.boot_mode = rp.power_state->prev_sleep_state; + + if (CONFIG(ELOG_BOOT_COUNT) + && rp.power_state->prev_sleep_state != ACPI_S3) + boot_count_increment(); + + /* Print ME state before MRC */ + intel_me_status(); + + /* Save ME HSIO version */ + intel_me_hsio_version(&rp.power_state->hsio_version, + &rp.power_state->hsio_checksum); + + /* Initialize RAM */ + raminit(&rp.pei_data); + + timestamp_add_now(TS_AFTER_INITRAM); + + romstage_handoff_init(rp.power_state->prev_sleep_state == ACPI_S3); + + mainboard_post_raminit(&rp);
platform_enter_postcar(); } @@ -117,33 +143,4 @@ romstage_main(base_timestamp, bist); }
-/* Entry from the mainboard. */ -void romstage_common(struct romstage_params *params) -{ - post_code(0x32); - - timestamp_add_now(TS_BEFORE_INITRAM); - - params->pei_data.boot_mode = params->power_state->prev_sleep_state; - -#if CONFIG(ELOG_BOOT_COUNT) - if (params->power_state->prev_sleep_state != ACPI_S3) - boot_count_increment(); -#endif - - /* Print ME state before MRC */ - intel_me_status(); - - /* Save ME HSIO version */ - intel_me_hsio_version(¶ms->power_state->hsio_version, - ¶ms->power_state->hsio_checksum); - - /* Initialize RAM */ - raminit(¶ms->pei_data); - - timestamp_add_now(TS_AFTER_INITRAM); - - romstage_handoff_init(params->power_state->prev_sleep_state == ACPI_S3); -} - void __weak mainboard_pre_console_init(void) {}