[coreboot-gerrit] Change in coreboot[master]: drivers/intel/fsp2_0: Add weak reservation for FSP-M memory

[Marshall Dawson (Code Review)]

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38700 )

Change subject: drivers/intel/fsp2_0: Add weak reservation for FSP-M memory
......................................................................

drivers/intel/fsp2_0: Add weak reservation for FSP-M memory

The function fsp_memory_init() is capable of executing in place or
as non-XIP.  For devices starting with DRAM enabled, this option
increases performance but requires the memory to be reserved later.

Add a weak function so the soc may save the base and size of the
memory consumed by FSP-M.

Signed-off-by: Marshall Dawson 
Change-Id: I04b2fff4074b720d1910ff21e1a1f841cfea8efb
---
M src/drivers/intel/fsp2_0/include/fsp/api.h
M src/drivers/intel/fsp2_0/memory_init.c
2 files changed, 10 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/38700/1

diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h
index 60adb98..a0366f6 100644
--- a/src/drivers/intel/fsp2_0/include/fsp/api.h
+++ b/src/drivers/intel/fsp2_0/include/fsp/api.h
@@ -50,6 +50,12 @@
 void fsp_temp_ram_exit(void);

/*
+ * When fsp_memory_init() runs non-XIP, and if it affects any DRAM, allow
+ * the soc to note the memory to be reserved.
+ */
+void fsp_reserve_fspm_mem(uintptr_t base, size_t size);
+
+/*
  * Load FSP-S from stage cache or CBFS. This allows SoCs to load FSPS-S
  * separately from calling silicon init. It might be required in cases where
  * stage cache is no longer available by the point SoC calls into silicon init.
diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c
index 455dfa5..3e9da8e 100644
--- a/src/drivers/intel/fsp2_0/memory_init.c
+++ b/src/drivers/intel/fsp2_0/memory_init.c
@@ -42,6 +42,8 @@
           CONFIG(VBOOT_STARTS_IN_BOOTBLOCK),
           "for TPM MRC hash functionality, vboot must start in bootblock");

+__weak void fsp_reserve_fspm_mem(uintptr_t base, size_t size) {}
+
 static void save_memory_training_data(bool s3wake, uint32_t fsp_version)
 {
    size_t  mrc_data_size;
@@ -356,6 +358,8 @@
    if (rdev_readat(rdev, (void *)fspm_begin, 0, fspm_end - fspm_begin) < 0)
    	return CB_ERR;

+	fsp_reserve_fspm_mem(fspm_begin, fspm_end - fspm_begin);
+
    return CB_SUCCESS;
 }