EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37685 )
Change subject: soc/intel/cannonlake: Move GPIO PM configuration to soc level ......................................................................
soc/intel/cannonlake: Move GPIO PM configuration to soc level
Enable/disable GPIO clock gating when enter/exit s0ix is common request on CNL/CML. Move it from board level to soc level.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I120f8369b8d3cf7ac821332bdfa124f6ed0570e9 --- M src/mainboard/google/drallion/variants/drallion/include/variant/acpi/mainboard.asl M src/mainboard/google/hatch/mainboard.asl M src/soc/intel/cannonlake/acpi/gpio.asl M src/soc/intel/cannonlake/acpi/lpit.asl 4 files changed, 31 insertions(+), 39 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/37685/1
diff --git a/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/mainboard.asl b/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/mainboard.asl index 608e4e0..b5cc268 100644 --- a/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/drallion/variants/drallion/include/variant/acpi/mainboard.asl @@ -16,15 +16,6 @@ #define CAM_EN GPP_B11 /* Active low */ #define TS_PD GPP_E7 #define HDMI_PD GPP_E16 -#include <intelblocks/gpio.h> - -Method (LOCL, 1, Serialized) -{ - For (Local0 = 0, Local0 < 5, Local0++) - { - _SB.PCI0.CGPM (Local0, Arg0) - } -}
/* Method called from LPIT prior to enter s0ix state */ Method (MS0X, 1) @@ -34,13 +25,11 @@ _SB.PCI0.STXS (CAM_EN) /* Turn off HDMI power */ _SB.PCI0.CTXS (HDMI_PD) - LOCL (MISCCFG_ENABLE_GPIO_PM_CONFIG) } Else { /* Turn on camera power */ _SB.PCI0.CTXS (CAM_EN) /* Turn on HDMI power */ _SB.PCI0.STXS (HDMI_PD) - LOCL (0) } }
@@ -53,12 +42,14 @@ _SB.PCI0.CTXS (TS_PD) /* Clear HDMI power to avoid leakage */ _SB.PCI0.CTXS (HDMI_PD) - LOCL (MISCCFG_ENABLE_GPIO_PM_CONFIG) + /* Enable GPIO PM */ + _SB.PCI0.LOCL (MISCCFG_ENABLE_GPIO_PM_CONFIG) }
/* Method called from _WAK prior to wakeup */ Method (MWAK, 1) { _SB.PCI0.LPCB.EC0.WAK (Arg0) - LOCL (0) + /* Disable GPIO PM */ + _SB.PCI0.LOCL (MISCCFG_ENABLE_GPIO_PM_CONFIG) } diff --git a/src/mainboard/google/hatch/mainboard.asl b/src/mainboard/google/hatch/mainboard.asl index dff1a75..6a72fe8 100644 --- a/src/mainboard/google/hatch/mainboard.asl +++ b/src/mainboard/google/hatch/mainboard.asl @@ -13,23 +13,13 @@ * GNU General Public License for more details. */
-#include <intelblocks/gpio.h> - -Method (LOCL, 1, Serialized) -{ - For (Local0 = 0, Local0 < 5, Local0++) - { - _SB.PCI0.CGPM (Local0, Arg0) - } -} - /* * Method called from _PTS prior to system sleep state entry * Enables dynamic clock gating for all 5 GPIO communities */ Method (MPTS, 1, Serialized) { - LOCL (MISCCFG_ENABLE_GPIO_PM_CONFIG) + _SB.PCI0.LOCL (MISCCFG_ENABLE_GPIO_PM_CONFIG) }
/* @@ -38,20 +28,6 @@ */ Method (MWAK, 1, Serialized) { - LOCL (0) + _SB.PCI0.LOCL (0) }
-/* - * S0ix Entry/Exit Notifications - * Called from _SB.LPID._DSM - */ -Method (MS0X, 1, Serialized) -{ - If (Arg0 == 1) { - /* S0ix Entry */ - LOCL (MISCCFG_ENABLE_GPIO_PM_CONFIG) - } Else { - /* S0ix Exit */ - LOCL (0) - } -} diff --git a/src/soc/intel/cannonlake/acpi/gpio.asl b/src/soc/intel/cannonlake/acpi/gpio.asl index 65332ad..aecb8c3 100644 --- a/src/soc/intel/cannonlake/acpi/gpio.asl +++ b/src/soc/intel/cannonlake/acpi/gpio.asl @@ -157,3 +157,12 @@ PCRO (Local0, GPIO_MISCCFG, And (Arg1, MISCCFG_ENABLE_GPIO_PM_CONFIG)) } } + +Method (LOCL, 1, Serialized) +{ + For (Local0 = 0, Local0 < 5, Local0++) + { + _SB.PCI0.CGPM (Local0, Arg0) + } +} + diff --git a/src/soc/intel/cannonlake/acpi/lpit.asl b/src/soc/intel/cannonlake/acpi/lpit.asl index 74d4fe6..bba7264 100644 --- a/src/soc/intel/cannonlake/acpi/lpit.asl +++ b/src/soc/intel/cannonlake/acpi/lpit.asl @@ -14,9 +14,19 @@ * GNU General Public License for more details. */
+#include <intelblocks/gpio.h> + External(_SB.MS0X, MethodObj) External(_SB.PCI0.LPCB.EC0.S0IX, MethodObj)
+Method (LOCL, 1, Serialized) +{ + For (Local0 = 0, Local0 < 5, Local0++) + { + _SB.PCI0.CGPM (Local0, Arg0) + } +} + scope(_SB) { Device(LPID) { @@ -73,6 +83,9 @@ If (CondRefOf (_SB.MS0X)) { _SB.MS0X(1) } + + /* Enable GPIO PM */ + _SB.PCI0.LOCL (MISCCFG_ENABLE_GPIO_PM_CONFIG) } /* * Function 6 - Low Power S0 Exit Notification @@ -87,6 +100,9 @@ If (CondRefOf (_SB.MS0X)) { _SB.MS0X(0) } + + /* Disable GPIO PM */ + _SB.PCI0.LOCL (0) } } Return(Buffer(One) {0x00})