[coreboot-gerrit] Change in coreboot[master]: soc/amd/common/lpc: Add SuperIO decode function

[Marshall Dawson (Code Review)]

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35271 )

Change subject: soc/amd/common/lpc: Add SuperIO decode function
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soc/amd/common/lpc: Add SuperIO decode function

The LPC-ISA bridge supports two ranges for SuperIO control registers.
Add a generic function to allow a mainboard to enable the appropriate
range.  Provide #define values that are more descriptive than the
register's field names.

Change-Id: Ic5445cfc137604cb1bb3ee3ea4c3a4ebdb9a9cab
Signed-off-by: Marshall Dawson 
---
M src/soc/amd/common/block/include/amdblocks/lpc.h
M src/soc/amd/common/block/lpc/lpc_util.c
2 files changed, 17 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/35271/1

diff --git a/src/soc/amd/common/block/include/amdblocks/lpc.h b/src/soc/amd/common/block/include/amdblocks/lpc.h
index 0f4f616..4b20ba7 100644
--- a/src/soc/amd/common/block/include/amdblocks/lpc.h
+++ b/src/soc/amd/common/block/include/amdblocks/lpc.h
@@ -75,6 +75,8 @@
 #define   LPC_WIDEIO0_ENABLE		BIT(2)
 #define   DECODE_ALTERNATE_SIO_ENABLE	BIT(1)
 #define   DECODE_SIO_ENABLE		BIT(0)
+#define     DECODE_SIO_4E4F		1
+#define     DECODE_SIO_2E2F		0
 #define   WIDEIO_RANGE_ERROR		-1

/* Assuming word access to higher word (register 0x4a) */
@@ -141,6 +143,8 @@
 void lpc_enable_port80(void);
 void lpc_enable_pci_port80(void);
 void lpc_enable_decode(uint32_t decodes);
+/* base = index/data I/O to enable.  0: 2e/2f, 1: 4e/4f */
+void lpc_enable_sio_decode(int base);
 uintptr_t lpc_spibase(void);
 void lpc_tpm_decode(void);
 void lpc_tpm_decode_spi(void);
diff --git a/src/soc/amd/common/block/lpc/lpc_util.c b/src/soc/amd/common/block/lpc/lpc_util.c
index 485eeda..27a5f4e 100644
--- a/src/soc/amd/common/block/lpc/lpc_util.c
+++ b/src/soc/amd/common/block/lpc/lpc_util.c
@@ -165,6 +165,19 @@
    pci_write_config8(_LPCB_DEV, LPC_IO_OR_MEM_DEC_EN_HIGH, byte);
 }

+/* base = index/data I/O to enable.  0: 2e/2f, 1: 4e/4f */
+void lpc_enable_sio_decode(int base)
+{
+	uint32_t decodes;
+
+	if (base > 1)
+		return;
+
+	decodes = pci_read_config32(_LPCB_DEV, LPC_IO_OR_MEM_DECODE_ENABLE);
+	decodes |= 1 << base;
+	pci_write_config32(_LPCB_DEV, LPC_IO_OR_MEM_DECODE_ENABLE, decodes);
+}
+
 void lpc_enable_decode(uint32_t decodes)
 {
    pci_write_config32(_LPCB_DEV, LPC_IO_PORT_DECODE_ENABLE, decodes);