[coreboot-gerrit] Change in coreboot[master]: soc/mediatek/mt8183: Improve the AC timing of DRAMC

[huayang duan (Code Review)]

Hello Duan huayang,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/39314

to review the following change.

Change subject: soc/mediatek/mt8183: Improve the AC timing of DRAMC
......................................................................

soc/mediatek/mt8183: Improve the AC timing of DRAMC

1. Set more AC timing items to make the system more stable.
2. Fix wrong setting of DRS config.

BUG=none
BRANCH=kukui
TEST=Boots correctly on Kukui

Change-Id: Ibd003582a3ffab1ae91f6378651c2c9e585c4676
Signed-off-by: Huayang Duan 
---
M src/soc/mediatek/mt8183/dramc_pi_basic_api.c
M src/soc/mediatek/mt8183/emi.c
2 files changed, 21 insertions(+), 10 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/39314/1

diff --git a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c
index 4033a91..89321a4 100644
--- a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c
+++ b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c
@@ -484,9 +484,10 @@

/* DRAM DRS DISABLE */
    	clrsetbits32(&ch[chn].ao.drsctrl,
-			(0x1 << 21) | (0x3f << 12) | (0xf << 8) | (0x1 << 6),
-			(0x1 << 19) | (0x3 << 12) | (0x8 << 8) |
-			(0x3 << 4) | (0x1 << 2) | (0x1 << 0));
+			(0x1 << 0) | (0x1 << 2) | (0x1 << 4) | (0x1 << 5) | (0x1 << 6) |
+			(0xf << 8) | (0x7f << 12) | (0x1 << 19) | (0x1 << 21),
+			(0x1 << 0) | (0x0 << 2) | (0x0 << 4) | (0x1 << 5) | (0x0 << 6) |
+			(0x8 << 8) | (0x3 << 12) | (0x1 << 19) | (0x0 << 21));
    	setbits32(&ch[chn].ao.dummy_rd, 0x3 << 26);
    }
    dramc_dqs_precalculation_preset();
diff --git a/src/soc/mediatek/mt8183/emi.c b/src/soc/mediatek/mt8183/emi.c
index 2310b5e..4a8f618 100644
--- a/src/soc/mediatek/mt8183/emi.c
+++ b/src/soc/mediatek/mt8183/emi.c
@@ -64,6 +64,8 @@
 struct optimize_ac_time {
    u8 rfc;
    u8 rfc_05t;
+	u8 rfc_pb;
+	u8 rfrc_pb05t;
    u16 tx_ref_cnt;
 };

@@ -336,19 +338,27 @@
 static void dramc_ac_timing_optimize(u8 freq_group)
 {
    struct optimize_ac_time rf_cab_opt[LP4X_DDRFREQ_MAX] = {
-		[LP4X_DDR1600] = {.rfc = 44, .rfc_05t = 0, .tx_ref_cnt = 62},
-		[LP4X_DDR2400] = {.rfc = 72, .rfc_05t = 0, .tx_ref_cnt = 91},
-		[LP4X_DDR3200] = {.rfc = 100, .rfc_05t = 0, .tx_ref_cnt = 119},
-		[LP4X_DDR3600] = {.rfc = 118, .rfc_05t = 1, .tx_ref_cnt = 138},
+		[LP4X_DDR1600] = {.rfc = 44, .rfc_05t = 0, .rfc_pb = 16,
+			.rfrc_pb05t = 0, .tx_ref_cnt = 62},
+		[LP4X_DDR2400] = {.rfc = 72, .rfc_05t = 0, .rfc_pb = 30,
+			.rfrc_pb05t = 0, .tx_ref_cnt = 91},
+		[LP4X_DDR3200] = {.rfc = 100, .rfc_05t = 0, .rfc_pb = 44,
+			.rfrc_pb05t = 0, .tx_ref_cnt = 119},
+		[LP4X_DDR3600] = {.rfc = 118, .rfc_05t = 1, .rfc_pb = 53,
+			.rfrc_pb05t = 1, .tx_ref_cnt = 138},
    };

for (size_t chn = 0; chn < CHANNEL_MAX; chn++) {
    	clrsetbits32(&ch[chn].ao.shu[0].actim[3],
    		0xff << 16, rf_cab_opt[freq_group].rfc << 16);
-		clrbits32(&ch[chn].ao.shu[0].ac_time_05t,
-			rf_cab_opt[freq_group].rfc_05t << 2);
-		clrsetbits32(&ch[chn].ao.shu[0].actim[4],
+		clrsetbits_le32(&ch[chn].ao.shu[0].ac_time_05t,
+			0x1 << 2, rf_cab_opt[freq_group].rfc_05t << 2);
+		clrsetbits_le32(&ch[chn].ao.shu[0].actim[4],
    		0x3ff << 0, rf_cab_opt[freq_group].tx_ref_cnt << 0);
+		clrsetbits_le32(&ch[chn].ao.shu[0].actim[3],
+			0xff << 0, rf_cab_opt[freq_group].rfc_pb << 0);
+		clrsetbits_le32(&ch[chn].ao.shu[0].ac_time_05t,
+			0x1 << 1, rf_cab_opt[freq_group].rfrc_pb05t << 1);
    }
 }