[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Add function to clear PMCON status bits

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61650 )

Change subject: soc/intel/skylake: Add function to clear PMCON status bits
......................................................................

soc/intel/skylake: Add function to clear PMCON status bits

This patch adds an SoC function to clear GEN_PMCON_A status bits to
align with other IA coreboot implementations.

Additionally, move the PMCON status bit clear operation to finalize.c
to cover any such chances where FSP-S NotifyPhase requested a global
reset and PMCON status bit remains set.

BUG=b:211954778
TEST=None.

Signed-off-by: Subrata Banik 
Change-Id: Ie786e6ba2daf88accb5d70be33de0abe593f8c53
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61650
Tested-by: build bot (Jenkins) 
Reviewed-by: Lean Sheng Tan 
---
M src/soc/intel/skylake/finalize.c
M src/soc/intel/skylake/include/soc/pm.h
M src/soc/intel/skylake/pmc.c
M src/soc/intel/skylake/pmutil.c
4 files changed, 20 insertions(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Lean Sheng Tan: Looks good to me, approved

diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c
index 5021595..afa1c02 100644
--- a/src/soc/intel/skylake/finalize.c
+++ b/src/soc/intel/skylake/finalize.c
@@ -65,6 +65,8 @@

/* Hide p2sb device as the OS must not change BAR0. */
    p2sb_hide();
+
+	pmc_clear_pmcon_sts();
 }

static void soc_lockdown(struct device *dev)
diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h
index f0ce146..51be0eb 100644
--- a/src/soc/intel/skylake/include/soc/pm.h
+++ b/src/soc/intel/skylake/include/soc/pm.h
@@ -189,4 +189,7 @@
 /* STM Support */
 uint16_t get_pmbase(void);

+/* Clear PMCON status bits */
+void pmc_clear_pmcon_sts(void);
+
 #endif
diff --git a/src/soc/intel/skylake/pmc.c b/src/soc/intel/skylake/pmc.c
index b9b85c2..61662d2 100644
--- a/src/soc/intel/skylake/pmc.c
+++ b/src/soc/intel/skylake/pmc.c
@@ -96,7 +96,6 @@
    config_deep_sx(config->deep_sx_config);

/* Clear registers that contain write-1-to-clear bits. */
-	pci_or_config32(dev, GEN_PMCON_A, 0);
    pci_or_config32(dev, GEN_PMCON_B, 0);
    pci_or_config32(dev, GEN_PMCON_B, 0);
    setbits32(pwrmbase + GBLRST_CAUSE0, 0);
diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c
index fe26ebf..ded44dc 100644
--- a/src/soc/intel/skylake/pmutil.c
+++ b/src/soc/intel/skylake/pmutil.c
@@ -265,3 +265,18 @@
    	reg8 |= SLEEP_AFTER_POWER_FAIL;
    pci_write_config8(dev, GEN_PMCON_B, reg8);
 }
+
+void pmc_clear_pmcon_sts(void)
+{
+	uint32_t reg_val;
+	const pci_devfn_t dev = PCH_DEV_PMC;
+
+	reg_val = pci_read_config32(dev, GEN_PMCON_A);
+	/*
+	 * Clear SUS_PWR_FLR, GBL_RST_STS, HOST_RST_STS, PWR_FLR bits
+	 * while retaining MS4V write-1-to-clear bit
+	 */
+	reg_val &= ~(MS4V);
+
+	pci_write_config32(dev, GEN_PMCON_A, reg_val);
+}