[coreboot-gerrit] Patch merged into coreboot/master: da3a146 arm64: Make SPSR exception masking on EL2 transition explicit

the following patch was just integrated into master:
commit da3a146caea1e85c9651a7f5889ad2a547d6f5e7
Author: Julius Werner 
Date:   Wed May 13 11:19:33 2015 -0700

arm64: Make SPSR exception masking on EL2 transition explicit

The configuration of SPSR bits that mask processor exceptions is kinda
    oddly hidden as an implict part of the transition() function right now.
    It would be odd but not impossible for programs to want to be entered
    with enabled exceptions, so let's move these bits to be explicitly set
    by the caller like the rest of SPSR instead.

Also clear up some macro names. The SPSR[I] bit is currently defined as
    SPSR_IRQ_ENABLE, which is particularly unfortunate since that bit
    actually *disables* (masks) interrupts. The fact that there is an
    additional SPSR_IRQ_MASK definition with the same value but a different
    purpose doesn't really help. There's rarely a point to have all three of
    xxx_SHIFT, xxx_MASK and xxx_VALUE macros for single-bit fields, so
    simplify this to a single definition per bit. (Other macros in
    lib_helpers.h should probably also be overhauled to conform, but I want
    to wait and see how many of them really stay relevant after upcoming
    changes first.)

BRANCH=None
    BUG=None
    TEST=None

Change-Id: Id126f70d365467e43b7f493c341542247e5026d2
    Signed-off-by: Patrick Georgi 
    Original-Commit-Id: 715600c83aef9794d1674e8c3b62469bdc57f297
    Original-Change-Id: I3edc4ee276feb8610a636ec7b4175706505d58bd
    Original-Signed-off-by: Julius Werner 
    Original-Reviewed-on: https://chromium-review.googlesource.com/270785
    Original-Reviewed-by: Aaron Durbin 
    Reviewed-on: http://review.coreboot.org/10250
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer

See http://review.coreboot.org/10250 for details.

-gerrit