[coreboot-gerrit] Change in coreboot[master]: soc/intel/jasperlake: Enable USB2 PHY SUS PG for s0ix qualification

[Krishna P Bhat D (Code Review)]

Hello build bot (Jenkins), Furquan Shaikh, Maulik V Vaghela, Justin TerAvest, Evan Green, Rizwan Qureshi, Ronak Kanabar, Patrick Rudolph, Divagar Mohandass, Karthik Ramasubramanian,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/49012

to look at the new patch set (#5).

Change subject: soc/intel/jasperlake: Enable USB2 PHY SUS PG for s0ix qualification
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soc/intel/jasperlake: Enable USB2 PHY SUS PG for s0ix qualification

USBSUSPGQDIS is a disqualifier bit which will allow platform
to enter s0ix even if USB2 PHY SUS is not power gated. Disabling this
bit will ensure that USB2 PHY SUS is power gated before entering s0ix.

BUG=b:175767084
BRANCH=dedede
TEST=s0ix works on drawcia and USB wake from s0ix works fine.

Change-Id: I20bad3f79141799c88a16272ea822b9e3dede504
Signed-off-by: Krishna Prasad Bhat 
---
M src/soc/intel/jasperlake/finalize.c
M src/soc/intel/jasperlake/include/soc/pmc.h
2 files changed, 16 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/49012/5