Attention is currently required from: Tarun Tuli, Subrata Banik.
Jérémy Compostella has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70303 )
Change subject: soc/intel/alderlake: Add romstage early graphics support ......................................................................
soc/intel/alderlake: Add romstage early graphics support
BUG=b:252792591 BRANCH=firmware-brya-14505.B TEST=TO-BE-COMPLETED
Change-Id: I727b28bbe180edc2574e09bf03f1534d6282bdb2 Signed-off-by: Jeremy Compostella jeremy.compostella@intel.com --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/romstage/Makefile.inc A src/soc/intel/alderlake/romstage/graphics.c 4 files changed, 109 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/70303/1
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 08d4132..a44cb98 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -205,6 +205,13 @@ hex default 0x10000
+if ROMSTAGE_GFX_GMA + +config GFX_GMA_DEFAULT_MMIO + default 0x81000000 + +endif # ROMSTAGE_GFX_GMA + # Intel recommends reserving the following resources per PCIe TBT root port, # from ADL BIOS Spec (doc #627270) Revision 0.6.0 Section 7.2.5.1.5 # - 42 buses diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index a732fe6..bd0b670 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -6,6 +6,7 @@ #include <drivers/i2c/designware/dw_i2c.h> #include <drivers/intel/gma/gma.h> #include <device/pci_ids.h> +#include <drivers/intel/gma/gma.h> #include <intelblocks/cfg.h> #include <intelblocks/gpio.h> #include <intelblocks/gspi.h> @@ -673,6 +674,11 @@
/* i915 struct for GMA backlight control */ struct i915_gpu_controller_info gfx; + + /* + * IGD panel configuration + */ + struct i915_gpu_panel_config panel_cfg; };
typedef struct soc_intel_alderlake_config config_t; diff --git a/src/soc/intel/alderlake/romstage/Makefile.inc b/src/soc/intel/alderlake/romstage/Makefile.inc index 99c1d2c..9714b62 100644 --- a/src/soc/intel/alderlake/romstage/Makefile.inc +++ b/src/soc/intel/alderlake/romstage/Makefile.inc @@ -4,3 +4,4 @@ romstage-y += ../../../../cpu/intel/car/romstage.c romstage-y += romstage.c romstage-y += systemagent.c +romstage-$(CONFIG_ROMSTAGE_GFX_GMA) += graphics.c diff --git a/src/soc/intel/alderlake/romstage/graphics.c b/src/soc/intel/alderlake/romstage/graphics.c new file mode 100644 index 0000000..a449699 --- /dev/null +++ b/src/soc/intel/alderlake/romstage/graphics.c @@ -0,0 +1,81 @@ +#include <arch/cpu.h> +#include <arch/mmio.h> +#include <cpu/x86/msr.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <drivers/intel/gma/i915_reg.h> +#include <intelblocks/early_graphics.h> +#include <soc/soc_chip.h> + +static void wait_txt_clear(void) +{ + struct cpuid_result cp = cpuid_ext(1, 0); + + /* Check if TXT is supported */ + if (!(cp.ecx & (1 << 6))) + return; + + /* Some TXT public bit */ + if (!(read32((void *)0xfed30010) & 1)) + return; + + /* Wait for TXT clear */ + while (!(read8((void *)0xfed40000) & (1 << 7))) + ; +} + +void early_graphics_soc_device_init(void) +{ + pci_devfn_t gfx_dev = PCI_DEV(0, 2, 0); + + /* Minimal GFX PCI initialization with BAR0 setup. */ + pci_or_config16(gfx_dev, PCI_COMMAND, PCI_COMMAND_MASTER); + pci_write_config32(gfx_dev, PCI_BASE_ADDRESS_0, + CONFIG_GFX_GMA_DEFAULT_MMIO); + pci_write_config16(gfx_dev, PCI_COMMAND, + PCI_COMMAND_IO | PCI_COMMAND_MEMORY); + + /* Ensure memory is unlocked. When the memory is locked, some accesses + to the graphics IP may unexpectedly fail. */ + msr_t msrval = { 0 }; + wait_txt_clear(); + wrmsr(0x2e6, msrval); +} + +void early_graphics_soc_panel_init(void) +{ + const struct soc_intel_alderlake_config *soc_conf; + const struct i915_gpu_panel_config *panel_cfg; + void *mmio = (void *)CONFIG_GFX_GMA_DEFAULT_MMIO; + uint32_t reg32; + unsigned int pwm_period, pwm_polarity, pwm_duty; + + soc_conf = config_of_soc(); + panel_cfg = &soc_conf->panel_cfg; + + reg32 = ((DIV_ROUND_UP(panel_cfg->cycle_delay_ms, 100) + 1) & 0x1f) << 4; + reg32 |= PANEL_POWER_RESET; + write32(mmio + PCH_PP_CONTROL, reg32); + + reg32 = ((panel_cfg->up_delay_ms * 10) & 0x1fff) << 16; + reg32 |= (panel_cfg->backlight_on_delay_ms * 10) & 0x1fff; + write32(mmio + PCH_PP_ON_DELAYS, reg32); + + reg32 = ((panel_cfg->down_delay_ms * 10) & 0x1fff) << 16; + reg32 |= (panel_cfg->backlight_off_delay_ms * 10) & 0x1fff; + write32(mmio + PCH_PP_OFF_DELAYS, reg32); + + if (!panel_cfg->backlight_pwm_hz) + return; + + /* Configure backlight */ + pwm_polarity = panel_cfg->backlight_polarity ? BXT_BLC_PWM_POLARITY : 0; + pwm_period = DIV_ROUND_CLOSEST(CONFIG_CPU_XTAL_HZ, + panel_cfg->backlight_pwm_hz); + pwm_duty = DIV_ROUND_CLOSEST(pwm_period, 2); /* Start with 50 % */ + write32(mmio + BXT_BLC_PWM_FREQ(0), pwm_period); + write32(mmio + BXT_BLC_PWM_CTL(0), pwm_polarity); + write32(mmio + BXT_BLC_PWM_DUTY(0), pwm_duty); +}