Rizwan Qureshi (rizwan.qureshi@intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16314
-gerrit
commit 28cbb8905720c1712ce814b5897763e5e996c9c8 Author: Barnali Sarkar barnali.sarkar@intel.com Date: Fri Aug 12 21:10:17 2016 +0530
skylake/kunimitsu: Add FSP 2.0 support in romstage
Populate mainboard related Memory Init Params i.e, SPD Rcomp values, DQ and DQs values.
setup stack and MTRRs after Dram initialization. This setup code is present in FSP1.1 driver, copy and reuse stack.c.
Populate SoC related Memory related params.
TEST=Build and boot kunimitsu, dram initialization done. problems in postcar observed.
Change-Id: I6eee23279b29f3e77912a719165f9f9c9ff42a8c Signed-off-by: Barnali Sarkar barnali.sarkar@intel.com --- src/mainboard/intel/kunimitsu/devicetree.cb | 3 + src/mainboard/intel/kunimitsu/romstage_fsp20.c | 86 ++++++++++- src/soc/intel/skylake/Makefile.inc | 6 + src/soc/intel/skylake/chip.h | 4 + src/soc/intel/skylake/include/fsp20/soc/romstage.h | 9 +- src/soc/intel/skylake/memmap.c | 20 ++- src/soc/intel/skylake/romstage/romstage_fsp20.c | 84 +++++++++- src/soc/intel/skylake/stack.c | 169 +++++++++++++++++++++ 8 files changed, 369 insertions(+), 12 deletions(-)
diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index 2aa3d95..a5789b0 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -187,6 +187,9 @@ chip soc/intel/skylake # Send an extra VR mailbox command for the PS4 exit issue register "SendVrMbxCmd" = "2"
+ # Enable/Disable VMX feature + register "VmxEnable" = "0" + # Use default SD card detect GPIO configuration register "sdcard_cd_gpio_default" = "GPP_A7"
diff --git a/src/mainboard/intel/kunimitsu/romstage_fsp20.c b/src/mainboard/intel/kunimitsu/romstage_fsp20.c index 10bdd21..152d35d 100644 --- a/src/mainboard/intel/kunimitsu/romstage_fsp20.c +++ b/src/mainboard/intel/kunimitsu/romstage_fsp20.c @@ -13,9 +13,93 @@ * GNU General Public License for more details. */
+#include <arch/byteorder.h> +#include <cbfs.h> +#include <console/console.h> +#include <fsp/api.h> +#include <gpio.h> +#include "gpio.h" #include <soc/romstage.h> +#include "spd/spd.h" +#include <string.h> + +#define RCOMP_TARGET_PARAMS 0x5
void mainboard_memory_init_params(struct FSPM_UPD *mupd) { - /* TODO: Read and copy SPD and fill up Rcomp and DQ param */ + struct FSP_M_CONFIG *mem_cfg; + mem_cfg = &mupd->FspmConfig; + char *spd_file; + size_t spd_file_len; + int spd_index, spd_span; + + /* DQ byte map */ + const u8 dq_map[2][12] = { + { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0 , + 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, + { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0 , + 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; + /* DQS CPU<>DRAM map */ + const u8 dqs_map[2][8] = { + { 0, 1, 3, 2, 6, 5, 4, 7 }, + { 2, 3, 0, 1, 6, 7, 4, 5 } }; + + /* Rcomp resistor */ + const u16 RcompResistor[3] = { 200, 81, 162 }; + + /* Rcomp target */ + static const u16 RcompTarget[RCOMP_TARGET_PARAMS] = { + 100, 40, 40, 23, 40 }; + + /*Strengthen the Rcomp Target Ctrl for 8GB K4E6E304EE -EGCF*/ + //static const u16 StrengthendRcompTarget[RCOMP_TARGET_PARAMS] = { + // 100, 40, 40, 21, 40 }; + + memcpy((void*)mem_cfg->DqByteMapCh0, dq_map, sizeof(dq_map)); + memcpy((void *)mem_cfg->DqsMapCpu2DramCh0, dqs_map, sizeof(dqs_map)); + memcpy((void*)mem_cfg->RcompResistor, RcompResistor, sizeof(RcompResistor)); + memcpy((void*)mem_cfg->RcompTarget, RcompTarget, sizeof(RcompTarget)); + mem_cfg->DqPinsInterleaved = 0; + + /* fill SPD Data */ + + /* PCH_MEM_CFG[3:0] */ + gpio_t spd_gpios[] = { + GPIO_MEM_CONFIG_0, + GPIO_MEM_CONFIG_1, + GPIO_MEM_CONFIG_2, + GPIO_MEM_CONFIG_3, + }; + + spd_index = gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); + + printk(BIOS_INFO, "SPD index %d\n", spd_index); + + /* Load SPD data from CBFS */ + spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, + &spd_file_len); + if (!spd_file) + die("SPD data not found."); + + /* make sure we have at least one SPD in the file. */ + if (spd_file_len < SPD_LEN) + die("Missing SPD data."); + + /* Make sure we did not overrun the buffer */ + if (spd_file_len < ((spd_index + 1) * SPD_LEN)) { + printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n"); + spd_index = 0; + } + + /* Assume same memory in both channels */ + spd_span = spd_index * SPD_LEN; + + mem_cfg->MemorySpdPtr00 = ( uint32_t )spd_file + spd_span; + mem_cfg->MemorySpdPtr10 = (uint32_t)spd_file + spd_span; + + printk(BIOS_DEBUG, " spd pointer address 00 -> 0x%8X \n" , (unsigned int)mem_cfg->MemorySpdPtr00); + printk(BIOS_DEBUG, " spd pointer address 00 -> 0x%8X \n" , (unsigned int)mem_cfg->MemorySpdPtr10); + printk(BIOS_DEBUG, " spd span -> 0x%8X \n" , (unsigned int) spd_file + spd_span); + + mem_cfg->MemorySpdDataLen = SPD_LEN; } diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index aa3da61..02b3ee8 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -42,6 +42,7 @@ romstage-y += pei_data.c romstage-y += pmutil.c romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c romstage-y += smbus_common.c +romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += stack.c romstage-y += tsc_freq.c romstage-$(CONFIG_UART_DEBUG) += uart_debug.c
@@ -104,6 +105,8 @@ CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1/skylake else CPPFLAGS_common += -I$(src)/soc/intel/skylake/include/fsp20 CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/skykabylake +$(CONFIG_FSP_M_CBFS)-options := --xip +$(CONFIG_FSP_S_CBFS)-options := --xip endif
# Currently used for microcode path. @@ -111,4 +114,7 @@ CPPFLAGS_common += -I3rdparty/blobs/mainboard/$(MAINBOARD_DIR)
ROMCCFLAGS := -mcpu=p4 -fno-simplify-phi -O2
+$(CONFIG_FSP_M_CBFS)-options := --xip +$(CONFIG_FSP_S_CBFS)-options := --xip + endif diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index a4dee51..62e28e6 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -359,6 +359,10 @@ struct soc_intel_skylake_config { * 011b - VR specific command sent for both MPS IMPV8 & PS4 exit issue */ u8 SendVrMbxCmd; + + /* Enable/Disable VMX feature */ + u8 VmxEnable; + /* Statically clock gate 8254 PIT. */ u8 clock_gate_8254;
diff --git a/src/soc/intel/skylake/include/fsp20/soc/romstage.h b/src/soc/intel/skylake/include/fsp20/soc/romstage.h index d48ac67..253ee32 100644 --- a/src/soc/intel/skylake/include/fsp20/soc/romstage.h +++ b/src/soc/intel/skylake/include/fsp20/soc/romstage.h @@ -22,9 +22,16 @@
asmlinkage void *car_stage_c_entry(void); void mainboard_memory_init_params(struct FSPM_UPD *mupd); - void systemagent_early_init(void); int smbus_read_byte(unsigned device, unsigned address); int early_spi_read_wpsr(u8 *sr); +void *setup_stack_and_mtrrs(void);
+/* Board type */ + enum BoardT{ + BOARD_TYPE_MOBILE = 0, + BOARD_TYPE_DESKTOP = 1, + BOARD_TYPE_ULT_ULX = 5, + BOARD_TYPE_SERVER = 7 +}; #endif /* _SOC_ROMSTAGE_H_ */ diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c index 96debfd..7c14598 100644 --- a/src/soc/intel/skylake/memmap.c +++ b/src/soc/intel/skylake/memmap.c @@ -144,31 +144,43 @@ u32 top_of_32bit_ram(void) const struct device *dev; const struct soc_intel_skylake_config *config;
+ top_of_ram = smm_region_start(); + /* * Check if Tseg has been initialized, we will use this as a flag * to check if the MRC is done, and only then continue to read the * PRMMR_BASE MSR. The system hangs if PRMRR_BASE MSR is read before * PRMRR_MASK MSR lock bit is set. */ - if (smm_region_start() == 0) + if (top_of_ram == 0) return 0;
dev = dev_find_slot(0, PCI_DEVFN(SA_DEV_SLOT_ROOT, 0)); config = dev->chip_info;
/* - * On Skylake, cbmem_top is offset down from PRMRR_BASE by reserved + * On Kabylake, cbmem_top is offset down from PRMRR_BASE by reserved * memory (128MiB) for CPU trace if enabled, then reserved memory (4KB) - * for PTT if enabled. PTT is in fact not used on Skylake platforms. + * for PTT if enabled. PTT is in fact not used on Kabylake platforms. * Refer to Fsp Integration Guide for the memory mapping layout. + * If SGX is enabled, then FSP updates PRMRR base & mask msr. + * Use value from PRMRR base msr to calculate top_of_ram. + * If PRMRR base is non-zero then top_of_ram is PRMRR base. */ + prmrr_base = rdmsr(UNCORE_PRMRR_PHYS_BASE_MSR); - top_of_ram = prmrr_base.lo; + if ( prmrr_base.lo != 0) + top_of_ram = prmrr_base.lo;
+ /* + * If ProbelessTrace is enabled then + * top_of_ram is top_of_ram minus TRACE_MEMORY_SIZE. + */ if (config->ProbelessTrace) top_of_ram -= TRACE_MEMORY_SIZE;
return top_of_ram; + }
void *cbmem_top(void) diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index 8a15a69..781bfa7 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -13,29 +13,101 @@ * GNU General Public License for more details. */
+#include <arch/cpu.h> +#include <arch/early_variables.h> +#include <arch/io.h> +#include <arch/symbols.h> +#include <assert.h> +#include <cpu/x86/mtrr.h> +#include <cbmem.h> +#include <chip.h> #include <console/console.h> +#include <device/pci_def.h> #include <fsp/util.h> +#include <soc/pci_devs.h> +#include <soc/pm.h> #include <soc/romstage.h> +#include <timestamp.h> +#include <vboot/vboot_common.h>
asmlinkage void *car_stage_c_entry(void) { - bool s3wake = false; + bool s3wake; + void *top_of_stack; + struct chipset_power_state *ps; + console_init(); - /* TODO: Add fill_powerstate and determine sleep state. */ + + /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */ + systemagent_early_init(); + + ps = fill_power_state(); + timestamp_add_now(TS_START_ROMSTAGE); + s3wake = ps->prev_sleep_state == ACPI_S3; fsp_memory_init(s3wake); - return NULL; + + top_of_stack = setup_stack_and_mtrrs(); + return top_of_stack; } + static void soc_memory_init_params(struct FSP_M_CONFIG *m_cfg) { - /* TODO: Fill SoC specific Memory init Params */ -} + const struct device *dev; + const struct soc_intel_skylake_config *config; + int i; + uint32_t mask = 0;
-void platform_fsp_memory_init_params_cb(struct FSPM_UPD *mupd){ + /* Set the parameters for MemoryInit */ + dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0)); + config = dev->chip_info; + /* + * Set IGD stolen size to 64MB. The FBC hardware for skylake does not + * have access to the bios_reserved range so it always assumes 8MB is + * used and so the kernel will avoid the last 8MB of the stolen window. + * With the default stolen size of 32MB(-8MB) there is not enough space + * for FBC to work with a high resolution panel. + */ + m_cfg->IgdDvmt50PreAlloc = 2; + m_cfg->MmioSize = 0x800; /* 2GB in MB */ + m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; + m_cfg->IedSize = CONFIG_IED_REGION_SIZE; + m_cfg->ProbelessTrace = config->ProbelessTrace; + m_cfg->EnableTraceHub = config->EnableTraceHub; + if (vboot_recovery_mode_enabled()) + m_cfg->SaGv = 0; /* Disable SaGv in recovery mode. */ + else + m_cfg->SaGv = config->SaGv; + m_cfg->UserBd = BOARD_TYPE_ULT_ULX; // boardtype=ULT + m_cfg->SpdProfileSelected=0; //default profile selected + m_cfg->RMT = config->Rmt; + m_cfg->DdrFreqLimit = config->DdrFreqLimit; + m_cfg->VmxEnable = config->VmxEnable; + for (i=0; i < ARRAY_SIZE(config->PcieRpEnable); i++){ + if (config->PcieRpEnable[i] == 1) + mask|=(1<<i); + } + m_cfg->PcieRpEnableMask = mask; +}
+void platform_fsp_memory_init_params_cb(struct FSPM_UPD *mupd) +{ struct FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; + struct FSP_M_TEST_CONFIG *m_t_cfg = &mupd->FspmTestConfig;
soc_memory_init_params(m_cfg); + + /* Enable DMI Virtual Channel for ME */ + m_t_cfg->DmiVcm = 0x01; + + /* Enable Sending DID to ME */ + m_t_cfg->SendDidMsg =0x01; + m_t_cfg->DidInitStat =0x01; + mainboard_memory_init_params(mupd); + + /* Reserve enough memory under TOLUD to save CBMEM header */ + mupd->FspmArchUpd.BootLoaderTolumSize = cbmem_overhead_size(); + }
__attribute__((weak)) void mainboard_memory_init_params(struct FSPM_UPD *mupd) diff --git a/src/soc/intel/skylake/stack.c b/src/soc/intel/skylake/stack.c new file mode 100644 index 0000000..31a6feb --- /dev/null +++ b/src/soc/intel/skylake/stack.c @@ -0,0 +1,169 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cbmem.h> +#include <console/console.h> +#include <cpu/x86/mtrr.h> +#include <soc/memmap.h> +#include <soc/romstage.h> +#include <stdlib.h> +#include <program_loading.h> +#include <soc/intel/common/util.h> + +static inline void *stack_push32(void *stack, uint32_t value) +{ + uint32_t *stack32 = stack; + + stack32 = &stack32[-1]; + *stack32 = value; + return stack32; +} + +/* + * setup_stack_and_mtrrs() determines the stack to use after + * cache-as-ram is torn down as well as the MTRR settings to use. + */ +void *setup_stack_and_mtrrs(void) +{ + size_t alignment; + uint32_t aligned_ram; + uint32_t mtrr_mask_upper; + uint32_t max_mtrrs; + uint32_t num_mtrrs; + uint32_t *slot; + unsigned long top_of_stack; + + /* Display the MTTRs */ + soc_display_mtrrs(); + + /* Top of stack needs to be aligned to a 8-byte boundary. */ + top_of_stack = romstage_ram_stack_top(); + slot = (void *)top_of_stack; + num_mtrrs = 0; + max_mtrrs = soc_get_variable_mtrr_count(NULL); + + /* + * The upper bits of the MTRR mask need to set according to the number + * of physical address bits. + */ + mtrr_mask_upper = (1 << ((cpuid_eax(0x80000008) & 0xff) - 32)) - 1; + alignment = mmap_region_granularity(); + aligned_ram = ALIGN_DOWN(romstage_ram_stack_bottom(), alignment); + + /* + * The order for each MTRR is value then base with upper 32-bits of + * each value coming before the lower 32-bits. The reasoning for + * this ordering is to create a stack layout like the following: + * + * +36: MTRR mask 1 63:32 + * +32: MTRR mask 1 31:0 + * +28: MTRR base 1 63:32 + * +24: MTRR base 1 31:0 + * +20: MTRR mask 0 63:32 + * +16: MTRR mask 0 31:0 + * +12: MTRR base 0 63:32 + * +8: MTRR base 0 31:0 + * +4: Number of MTRRs to setup (described above) + * +0: Number of variable MTRRs to clear + */ + + /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ + slot = stack_push32(slot, mtrr_mask_upper); /* upper mask */ + slot = stack_push32(slot, ~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID); + slot = stack_push32(slot, 0); /* upper base */ + slot = stack_push32(slot, 0 | MTRR_TYPE_WRBACK); + num_mtrrs++; + + /* + * +-------------------------+ Top of RAM (aligned) + * | System Management Mode | + * | code and data | Length: CONFIG_TSEG_SIZE + * | (TSEG) | + * +-------------------------+ SMM base (aligned) + * | | + * | Chipset Reserved Memory | Length: Multiple of CONFIG_TSEG_SIZE + * | | + * +-------------------------+ top_of_ram (aligned) + * | | + * | CBMEM Root | + * | | + * +-------------------------+ + * | | + * | FSP Reserved Memory | + * | | + * +-------------------------+ + * | | + * | Various CBMEM Entries | + * | | + * +-------------------------+ top_of_stack (8 byte aligned) + * | | + * | stack (CBMEM Entry) | + * | | + * +-------------------------+ + */ + + /* + * Cache the stack and the other CBMEM entries as well as part or all + * of the FSP reserved memory region. + */ + slot = stack_push32(slot, mtrr_mask_upper); /* upper mask */ + slot = stack_push32(slot, ~(alignment - 1) | MTRR_PHYS_MASK_VALID); + slot = stack_push32(slot, 0); /* upper base */ + slot = stack_push32(slot, aligned_ram | MTRR_TYPE_WRBACK); + num_mtrrs++; + +#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) + void *smm_base; + size_t smm_size; + uint32_t tseg_base; + + /* + * Cache the TSEG region at the top of ram. This region is not + * restricted to SMM mode until SMM has been relocated. By setting + * the region to cacheable it provides faster access when relocating + * the SMM handler as well as using the TSEG region for other purposes. + */ + smm_region(&smm_base, &smm_size); + tseg_base = (uint32_t)smm_base; + slot = stack_push32(slot, mtrr_mask_upper); /* upper mask */ + slot = stack_push32(slot, ~(alignment - 1) | MTRR_PHYS_MASK_VALID); + slot = stack_push32(slot, 0); /* upper base */ + slot = stack_push32(slot, tseg_base | MTRR_TYPE_WRBACK); + num_mtrrs++; +#endif + + /* Cache the ROM as WP just below 4GiB. */ + slot = stack_push32(slot, mtrr_mask_upper); /* upper mask */ + slot = stack_push32(slot, ~(CONFIG_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID); + slot = stack_push32(slot, 0); /* upper base */ + slot = stack_push32(slot, ~(CONFIG_ROM_SIZE - 1) | MTRR_TYPE_WRPROT); + num_mtrrs++; + + /* Validate the MTRR usage */ + if (num_mtrrs > max_mtrrs) { + printk(BIOS_ERR, "MTRRs: max = %d, used = %d, available=%d", + max_mtrrs, num_mtrrs, max_mtrrs - num_mtrrs); + die("ERROR - MTRR use count incorrect!\n"); + } + + /* + * Save the number of MTRRs to setup and clear. Return the stack + * location pointing to the number of MTRRs. + */ + slot = stack_push32(slot, num_mtrrs); + slot = stack_push32(slot, max_mtrrs); + return slot; +}