Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38978 )
Change subject: mb/acer: add Aspire ES1-572 and Extensa 2540 (Compal LA-E061P) ......................................................................
Patch Set 10:
(11 comments)
https://review.coreboot.org/c/coreboot/+/38978/7//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/38978/7//COMMIT_MSG@37 PS7, Line 37: - Touchpad. Hangs off either EC or some I2C controller and needs ACPI.
Well, it's connected to the EC's PS/2 port 3 (according to the kb9012 ds). […]
Done
https://review.coreboot.org/c/coreboot/+/38978/5/src/mainboard/acer/es1-572/... File src/mainboard/acer/es1-572/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/38978/5/src/mainboard/acer/es1-572/... PS5, Line 223: register "SendVrMbxCmd" = "2"
What I could find out: There are issues with (some) IMVP8 controllers. […]
Done
https://review.coreboot.org/c/coreboot/+/38978/7/src/mainboard/acer/es1-572/... File src/mainboard/acer/es1-572/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/38978/7/src/mainboard/acer/es1-572/... PS7, Line 37: register "SataTestMode" = "1"
Yes, I do want that.
Done
https://review.coreboot.org/c/coreboot/+/38978/7/src/mainboard/acer/es1-572/... PS7, Line 40: register "SataPortsDevSlp[0]" = "0" : register "SataPortsDevSlp[1]" = "0" :
schematics say nooooo ;)
Done
https://review.coreboot.org/c/coreboot/+/38978/7/src/mainboard/acer/es1-572/... PS7, Line 42: SataSpeedLimit" = "3"
speed 3 (also matches 0) is the default already
Done
https://review.coreboot.org/c/coreboot/+/38978/7/src/mainboard/acer/es1-572/... PS7, Line 86: register "usb2_ports[3]" = "USB2_PORT_EMPTY" # N/C
not required anymore; drop; see CB:45106
Done
https://review.coreboot.org/c/coreboot/+/38978/7/src/mainboard/acer/es1-572/... PS7, Line 93: register "usb3_ports[1]" = "USB3_PORT_EMPTY" # N/C : register "usb3_ports[2]" = "USB3_PORT_EMPTY" # N/C : register "usb3_ports[3]" = "USB3_PORT_EMPTY" # N/C :
not required anymore; drop them; see CB:45106
Done
https://review.coreboot.org/c/coreboot/+/38978/7/src/mainboard/acer/es1-572/... PS7, Line 108: device pci 04.0 off end # CPU Thermal Subsystem
it's not about EC ACPI and it's not only about DPTF. […]
Done
https://review.coreboot.org/c/coreboot/+/38978/7/src/mainboard/acer/es1-572/... File src/mainboard/acer/es1-572/gpio.c:
https://review.coreboot.org/c/coreboot/+/38978/7/src/mainboard/acer/es1-572/... PS7, Line 7: #define PAD_CFG_NF_BUF_TRIG(a, b, c, d, e, f) PAD_CFG_NF(a, b, c, d)
I'd rather re-do the whole file.
Done
https://review.coreboot.org/c/coreboot/+/38978/7/src/mainboard/acer/es1-572/... PS7, Line 144: _PAD_CFG_STRUCT(GPP_B3, : PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | : PAD_CFG0_TRIG_LEVEL | PAD_CFG0_RX_POL_YES | : PAD_BUF(TX_DISABLE), : PAD_PULL(NONE)), :
I'll re-do the whole file
Done
https://review.coreboot.org/c/coreboot/+/38978/7/src/mainboard/acer/es1-572/... File src/mainboard/acer/es1-572/romstage.c:
https://review.coreboot.org/c/coreboot/+/38978/7/src/mainboard/acer/es1-572/... PS7, Line 32: /* These settings are most likely useless if using a release build of FSP */ : mem_cfg->PcdDebugInterfaceFlags = 2; /* 2: Enable UART */ : mem_cfg->PcdSerialIoUartNumber = 2; /* 2: Use UART #2 */ : mem_cfg->PcdSerialDebugBaudRate = 7; /* 7: 115200 baud */ : mem_cfg->PcdSerialDebugLevel = 3; /* 3: Log <= Info */ :
well, that's all fsp defaults (except the TH bit in PcdSerialIoUartNumber, which doesn't do anything […]
Done