[coreboot-gerrit] [XS] Change in coreboot[main]: soc/intel/alderlake/tcss: Add definition of IOM_READY bit

[Michał Żygowski (Code Review)]

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Nick Vaccaro, Subrata Banik.

Hello Dinesh Gehlot, Kapil Porwal, Nick Vaccaro, Nico Huber, Subrata Banik, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/83356?usp=email

to look at the new patch set (#4).

Change subject: soc/intel/alderlake/tcss: Add definition of IOM_READY bit
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soc/intel/alderlake/tcss: Add definition of IOM_READY bit

Add definition of the IOM_READY bit in the IOM_TYPEC_STATUS_1
register. Needed by Protectli VP66XX boards to poll for this bit
for about 2 seconds before FSP Silicon Init to have USB functionality.
ME is supposed to start fetching and executing the TCSS IPs FW right
after DRAM Init Done message, which happens after MRC. For most
platforms the time interval between the end of MemoryInit and start of
SiliconInit is enough for IOM_READY to get set.

TEST=Poll the IOM_READY bit on VP66XX platform and observe the
TCSS XHCI is up in lspci.

Change-Id: If868a77852468ebb73526b1571191cbdeb1804b9
Signed-off-by: Michał Żygowski 
---
M src/soc/intel/alderlake/include/soc/tcss.h
1 file changed, 4 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/83356/4