2 Feb
2022
2 Feb
'22
4:17 p.m.
Attention is currently required from: Maulik V Vaghela, Meera Ravindranath, Sridhar Siricilla, Nick Vaccaro. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61266 )
Change subject: mb/google/brya/variants/gimble: Disable PCIE RP 6 and TCSS Port 1 ......................................................................
Patch Set 3: Code-Review+2
--
To view, visit https://review.coreboot.org/c/coreboot/+/61266
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I0e7ae72620da39fc18ff253c440d006e83c576f3
Gerrit-Change-Number: 61266
Gerrit-PatchSet: 3
Gerrit-Owner: Meera Ravindranath meera.ravindranath@intel.com
Gerrit-Reviewer: Mark Hsieh mark_hsieh@wistron.corp-partner.google.com
Gerrit-Reviewer: Maulik V Vaghela maulik.v.vaghela@intel.com
Gerrit-Reviewer: Nick Vaccaro nvaccaro@google.com
Gerrit-Reviewer: Sridhar Siricilla sridhar.siricilla@intel.com
Gerrit-Reviewer: Tim Wawrzynczak twawrzynczak@chromium.org
Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org
Gerrit-CC: Anfernee Chen anfernee_chen@wistron.corp-partner.google.com
Gerrit-CC: Casper Chang casper_chang@wistron.corp-partner.google.com
Gerrit-CC: Kane Chen kane.chen@intel.com
Gerrit-CC: Malik Hsu malik_hsu@wistron.corp-partner.google.com
Gerrit-CC: Paul Menzel paulepanter@mailbox.org
Gerrit-CC: Scott Chao scott_chao@wistron.corp-partner.google.com
Gerrit-Attention: Maulik V Vaghela maulik.v.vaghela@intel.com
Gerrit-Attention: Meera Ravindranath meera.ravindranath@intel.com
Gerrit-Attention: Sridhar Siricilla sridhar.siricilla@intel.com
Gerrit-Attention: Nick Vaccaro nvaccaro@google.com
Gerrit-Comment-Date: Wed, 02 Feb 2022 16:17:57 +0000
Gerrit-HasComments: No
Gerrit-Has-Labels: Yes
Gerrit-MessageType: comment