[coreboot-gerrit] Change in coreboot[master]: mc_apl2: Enable UART for GDB debugging

[Werner Zeh (Code Review)]

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36025 )

Change subject: mc_apl2: Enable UART for GDB debugging
......................................................................

mc_apl2: Enable UART for GDB debugging

Change-Id: Idd4504d8f11aa78196d6d87d0fa13338b708f53e
Signed-off-by: Werner Zeh 
---
M src/mainboard/siemens/mc_apl1/romstage.c
1 file changed, 54 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/36025/1

diff --git a/src/mainboard/siemens/mc_apl1/romstage.c b/src/mainboard/siemens/mc_apl1/romstage.c
index 1483636..bd21dd1 100644
--- a/src/mainboard/siemens/mc_apl1/romstage.c
+++ b/src/mainboard/siemens/mc_apl1/romstage.c
@@ -127,3 +127,57 @@
    memupd->FspmConfig.MrcDataSaving = 0x0;
    memupd->FspmConfig.MrcFastBoot   = 0x1;
 }
+#if CONFIG(GDB_STUB)
+#include <device/device.h>
+#include <device/pci.h>
+#include <arch/io.h>
+#include <soc/romstage.h>
+
+/*
+ * We need a way to hook in right after the romstage has been finished
+ * to enable the UART on CUPER. This must happen for sure before ramstage
+ * starts and the code is mainboard dependent. Due to FSP 2.0 there are no
+ * other mainboard-hooks for romstage beside the ones for DRAM parameter setup
+ * and this one. So use this hook now for the needed code.
+ * This is noting to release, just for internal usage.
+ */
+#define FPGA_PCI_BUS            1
+#define FPGA_TEMP_BAR0          0xf7000000
+#if CONFIG(BOARD_SIEMENS_MC_APL2)
+#define CUPER_ROOT_DEV		(PCI_DEV(0, 0x13, 0x01))
+#endif
+#define CUPER_PCI_DEV		(PCI_DEV(FPGA_PCI_BUS, 0, 0))
+void mainboard_save_dimm_info(void)
+{
+	uint32_t reg;
+
+	if (CONFIG(BOARD_SIEMENS_MC_APL2)) {
+		/* First set up root port bridge to get access to the FPGA. */
+		 /* Set secondary bus temporary. */
+		pci_write_config32(CUPER_ROOT_DEV, PCI_PRIMARY_BUS,
+				    FPGA_PCI_BUS << 16 | FPGA_PCI_BUS << 8);
+		/* Define an address window to forward to the secondary bus. */
+		pci_write_config32(CUPER_ROOT_DEV, PCI_MEMORY_BASE,
+				    (FPGA_TEMP_BAR0 | (FPGA_TEMP_BAR0 >> 16)));
+		/* Enable memory mapped transfers */
+		pci_write_config32(CUPER_ROOT_DEV, PCI_COMMAND,
+				    PCI_COMMAND_MEMORY);
+		/* Now the FPGA is visible on bus 1, dev 0, function 0. */
+		pci_write_config32(CUPER_PCI_DEV, PCI_BASE_ADDRESS_0,
+					FPGA_TEMP_BAR0);
+		pci_write_config32(CUPER_PCI_DEV, PCI_COMMAND,
+					PCI_COMMAND_MEMORY);
+		/* Now we can reach MMIO mapped registers in CUPER */
+		reg = read32((void *)(FPGA_TEMP_BAR0 + 0xbc));
+		reg |= (1 << 10);
+		write32((void *)(FPGA_TEMP_BAR0 + 0xbc), reg);
+		/* Now delete all the changes made in config space so that
+		 * the PCI enumerator can do its work. */
+		pci_write_config32(CUPER_PCI_DEV, PCI_BASE_ADDRESS_0, 0);
+		pci_write_config32(CUPER_PCI_DEV, PCI_COMMAND, 0);
+		pci_write_config32(CUPER_ROOT_DEV, PCI_PRIMARY_BUS, 0x0);
+		pci_write_config32(CUPER_ROOT_DEV, PCI_MEMORY_BASE, 0);
+		pci_write_config32(CUPER_ROOT_DEV, PCI_COMMAND, 0);
+	}
+}
+#endif