[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake: Refactor SoC code to maintain CPU and PCH PCIE RPs

[Angel Pons (Code Review)]

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Patrick Rudolph, EricR Lai.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49136 )

Change subject: soc/intel/alderlake: Refactor SoC code to maintain CPU and PCH PCIE RPs
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Patch Set 5: Code-Review+1

(2 comments)

File src/mainboard/intel/adlrvp/devicetree.cb:

https://review.coreboot.org/c/coreboot/+/49136/comment/feedf21f_90b5ad61 
PS5, Line 75: 1
Code says CLK 3. Also, I would not say `PEG CLK` since the clocks come from the PCH, just `CLK` is enough.

https://review.coreboot.org/c/coreboot/+/49136/comment/9c456168_2919d342 
PS5, Line 79: 2
Code says CLK 4