[coreboot-gerrit] Change in coreboot[master]: sb,soc/intel: Set IOAPIC max entries before APIC ID

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55308 )

Change subject: sb,soc/intel: Set IOAPIC max entries before APIC ID
......................................................................

sb,soc/intel: Set IOAPIC max entries before APIC ID

This allows to replace set_ioapic_id() call with setup_ioapic()
that also clears redirection table entries.

Change-Id: I854f19c997a96bcdccb11a0906431e3291788cb6
Signed-off-by: Kyösti Mälkki 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55308
Tested-by: build bot (Jenkins) 
Reviewed-by: Arthur Heymans 
---
M src/soc/intel/broadwell/pch/lpc.c
M src/soc/intel/common/block/lpc/lpc_lib.c
M src/soc/intel/denverton_ns/lpc.c
M src/southbridge/intel/bd82x6x/lpc.c
M src/southbridge/intel/ibexpeak/lpc.c
M src/southbridge/intel/lynxpoint/lpc.c
6 files changed, 13 insertions(+), 12 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Arthur Heymans: Looks good to me, approved

diff --git a/src/soc/intel/broadwell/pch/lpc.c b/src/soc/intel/broadwell/pch/lpc.c
index 40cc61e..a3de7ac 100644
--- a/src/soc/intel/broadwell/pch/lpc.c
+++ b/src/soc/intel/broadwell/pch/lpc.c
@@ -29,11 +29,11 @@
    pci_write_config16(dev, LPC_IBDF,
    	PCH_IOAPIC_PCI_BUS << 8 | PCH_IOAPIC_PCI_SLOT << 3);

-	set_ioapic_id(VIO_APIC_VADDR, 0x02);
-
    /* affirm full set of redirection table entries ("write once") */
    /* PCH-LP has 40 redirection entries */
    ioapic_set_max_vectors(VIO_APIC_VADDR, 40);
+
+	set_ioapic_id(VIO_APIC_VADDR, 0x02);
 }

static void enable_hpet(struct device *dev)
diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c
index c2278df..43434df 100644
--- a/src/soc/intel/common/block/lpc/lpc_lib.c
+++ b/src/soc/intel/common/block/lpc/lpc_lib.c
@@ -280,10 +280,10 @@
 /* Enable PCH IOAPIC */
 void pch_enable_ioapic(void)
 {
-	set_ioapic_id((void *)IO_APIC_ADDR, 0x02);
-
    /* affirm full set of redirection table entries ("write once") */
    ioapic_set_max_vectors(VIO_APIC_VADDR, PCH_REDIR_ETR);
+
+	set_ioapic_id((void *)IO_APIC_ADDR, 0x02);
 }

static const uint8_t pch_interrupt_routing[PIRQ_COUNT] = {
diff --git a/src/soc/intel/denverton_ns/lpc.c b/src/soc/intel/denverton_ns/lpc.c
index 7f47e5e..f0a7058 100644
--- a/src/soc/intel/denverton_ns/lpc.c
+++ b/src/soc/intel/denverton_ns/lpc.c
@@ -31,10 +31,10 @@
  */
 static void pch_enable_ioapic(struct device *dev)
 {
-	set_ioapic_id((void *)IO_APIC_ADDR, IO_APIC0);
-
    /* affirm full set of redirection table entries ("write once") */
    ioapic_set_max_vectors(VIO_APIC_VADDR, PCH_REDIR_ETR);
+
+	set_ioapic_id((void *)IO_APIC_ADDR, IO_APIC0);
 }

/* interrupt router lookup for internal devices */
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index b1f5ec8..51d6b07 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -41,10 +41,10 @@
    pci_write_config16(dev, LPC_IBDF,
    	PCH_IOAPIC_PCI_BUS << 8 | PCH_IOAPIC_PCI_SLOT << 3);

-	set_ioapic_id(VIO_APIC_VADDR, 0x02);
-
    /* affirm full set of redirection table entries ("write once") */
    ioapic_lock_max_vectors(VIO_APIC_VADDR);
+
+	set_ioapic_id(VIO_APIC_VADDR, 0x02);
 }

static void pch_enable_serial_irqs(struct device *dev)
diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c
index f1cf7a3..fa53db2 100644
--- a/src/southbridge/intel/ibexpeak/lpc.c
+++ b/src/southbridge/intel/ibexpeak/lpc.c
@@ -34,10 +34,10 @@
  */
 static void pch_enable_ioapic(struct device *dev)
 {
-	set_ioapic_id(VIO_APIC_VADDR, 0x01);
-
    /* affirm full set of redirection table entries ("write once") */
    ioapic_lock_max_vectors(VIO_APIC_VADDR);
+
+	set_ioapic_id(VIO_APIC_VADDR, 0x01);
 }

static void pch_enable_serial_irqs(struct device *dev)
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index ef75d2f..72f6d80 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -35,14 +35,15 @@
    pci_write_config16(dev, LPC_IBDF,
    	PCH_IOAPIC_PCI_BUS << 8 | PCH_IOAPIC_PCI_SLOT << 3);

-	set_ioapic_id(VIO_APIC_VADDR, 0x02);
-
    /* affirm full set of redirection table entries ("write once") */
    /* PCH-LP has 40 redirection entries */
    if (pch_is_lp())
    	ioapic_set_max_vectors(VIO_APIC_VADDR, 40);
    else
    	ioapic_lock_max_vectors(VIO_APIC_VADDR);
+
+	set_ioapic_id(VIO_APIC_VADDR, 0x02);
+
 }

static void pch_enable_serial_irqs(struct device *dev)